| 2005 |
|---|
| 5 | EE | Atsushi Kurokawa,
Masaharu Yamamoto,
Nobuto Ono,
Tetsuro Kage,
Yasuaki Inoue,
Hiroo Masuda:
Capacitance and Yield Evaluations Using a 90-nm Process Technology Based on the Dense Power-Ground Interconnect Architecture.
ISQED 2005: 153-158 |
| 4 | EE | Atsushi Kurokawa,
Toshiki Kanamoto,
Tetsuya Ibe,
Akira Kasebe,
Wei Fong Chang,
Tetsuro Kage,
Yasuaki Inoue,
Hiroo Masuda:
Dummy Filling Methods for Reducing Interconnect Capacitance and Number of Fills.
ISQED 2005: 586-591 |
| 3 | EE | Atsushi Kurokawa,
Toshiki Kanamoto,
Tetsuya Ibe,
Akira Kasebe,
Wei Fong Chang,
Tetsuro Kage,
Yasuaki Inoue,
Hiroo Masuda:
Efficient Dummy Filling Methods to Reduce Interconnect Capacitance and Number of Dummy Metal Fills.
IEICE Transactions 88-A(12): 3471-3478 (2005) |
| 2004 |
|---|
| 2 | EE | Chieki Mizuta,
Jiro Iwai,
Ken Machida,
Tetsuro Kage,
Hiroo Masuda:
Large-scale linear circuit simulation with an inversed inductance matrix.
ASP-DAC 2004: 511-516 |
| 1 | EE | Atsushi Kurokawa,
Nobuto Ono,
Tetsuro Kage,
Hiroo Masuda:
DEPOGIT: dense power-ground interconnect architecture for physical design integrity.
ASP-DAC 2004: 517-522 |
