2005 | ||
---|---|---|
4 | EE | Vishak Venkatraman, Wayne Burleson: Robust Multi-Level Current-Mode On-Chip Interconnect Signaling in the Presence of Process Variations. ISQED 2005: 522-527 |
3 | EE | Vishak Venkatraman, Wayne Burleson: Impact of Process Variations on Multi-Level Signaling for On-Chip Interconnects. VLSI Design 2005: 362-367 |
2004 | ||
2 | EE | Vishak Venkatraman, Atul Maheshwari, Wayne Burleson: Mitigating static power in current-sensed interconnects. ACM Great Lakes Symposium on VLSI 2004: 224-229 |
1 | EE | Vishak Venkatraman, Andrew Laffely, Jinwook Jang, Hempraveen Kukkamalla, Zhi Zhu, Wayne Burleson: NoCIC: a spice-based interconnect planning tool emphasizing aggressive on-chip interconnect circuit methods. SLIP 2004: 69-75 |
1 | Wayne P. Burleson (Wayne Burleson) | [1] [2] [3] [4] |
2 | Jinwook Jang | [1] |
3 | Hempraveen Kukkamalla | [1] |
4 | Andrew Laffely | [1] |
5 | Atul Maheshwari | [2] |
6 | Zhi Zhu | [1] |