2008 |
17 | EE | Atsushi Kurokawa,
Hiroshi Fujita,
Tetsuya Ibe:
Prevention in a Chip of EMI Noise Caused by X'tal Oscillator.
IEICE Transactions 91-A(4): 1077-1083 (2008) |
2007 |
16 | EE | Zhangcai Huang,
Hong Yu,
Atsushi Kurokawa,
Yasuaki Inoue:
Modeling the Overshooting Effect for CMOS Inverter in Nanometer Technologies.
ASP-DAC 2007: 565-570 |
2006 |
15 | EE | Kenichi Shinkai,
Masanori Hashimoto,
Atsushi Kurokawa,
Takao Onoye:
A gate delay model focusing on current fluctuation over wide-range of process and environmental variability.
ICCAD 2006: 47-53 |
14 | EE | Toshiki Kanamoto,
Shigekiyo Akutsu,
Tamiyo Nakabayashi,
Takahiro Ichinomiya,
Koutaro Hachiya,
Atsushi Kurokawa,
Hiroshi Ishikawa,
Sakae Muromoto,
Hiroyuki Kobayashi,
Masanori Hashimoto:
Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation.
IEICE Transactions 89-A(12): 3666-3670 (2006) |
13 | EE | Zhangcai Huang,
Atsushi Kurokawa,
Yun Yang,
Hong Yu,
Yasuaki Inoue:
Modeling the Influence of Input-to-Output Coupling Capacitance on CMOS Inverter Delay.
IEICE Transactions 89-A(4): 840-846 (2006) |
12 | EE | Atsushi Kurokawa,
Akira Kasebe,
Toshiki Kanamoto,
Yun Yang,
Zhangcai Huang,
Yasuaki Inoue,
Hiroo Masuda:
Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills.
IEICE Transactions 89-A(4): 847-855 (2006) |
11 | EE | Atsushi Kurokawa,
Hiroo Masuda,
Junko Fujii,
Toshinori Inoshita,
Akira Kasebe,
Zhangcai Huang,
Yasuaki Inoue:
Determination of Interconnect Structural Parameters for Best- and Worst-Case Delays.
IEICE Transactions 89-A(4): 856-864 (2006) |
2005 |
10 | EE | Zhangcai Huang,
Atsushi Kurokawa,
Yasuaki Inoue:
Effective capacitance for gate delay with RC loads.
ISCAS (3) 2005: 2795-2798 |
9 | EE | Atsushi Kurokawa,
Masaharu Yamamoto,
Nobuto Ono,
Tetsuro Kage,
Yasuaki Inoue,
Hiroo Masuda:
Capacitance and Yield Evaluations Using a 90-nm Process Technology Based on the Dense Power-Ground Interconnect Architecture.
ISQED 2005: 153-158 |
8 | EE | Atsushi Kurokawa,
Toshiki Kanamoto,
Tetsuya Ibe,
Akira Kasebe,
Wei Fong Chang,
Tetsuro Kage,
Yasuaki Inoue,
Hiroo Masuda:
Dummy Filling Methods for Reducing Interconnect Capacitance and Number of Fills.
ISQED 2005: 586-591 |
7 | EE | Zhangcai Huang,
Atsushi Kurokawa,
Yasuaki Inoue,
Junfa Mao:
A Novel Model for Computing the Effective Capacitance of CMOS Gates with Interconnect Loads.
IEICE Transactions 88-A(10): 2562-2569 (2005) |
6 | EE | Atsushi Kurokawa,
Toshiki Kanamoto,
Akira Kasebe,
Yasuaki Inoue,
Hiroo Masuda:
A Practical Approach for Efficiently Extracting Interconnect Capacitances with Floating Dummy Fills.
IEICE Transactions 88-A(11): 3180-3187 (2005) |
5 | EE | Zhangcai Huang,
Atsushi Kurokawa,
Jun Pan,
Yasuaki Inoue:
Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew.
IEICE Transactions 88-A(12): 3367-3374 (2005) |
4 | EE | Yun Yang,
Atsushi Kurokawa,
Yasuaki Inoue,
Wenqing Zhao:
Efficient Large Scale Integration Power/Ground Network Optimization Based on Grid Genetic Algorithm.
IEICE Transactions 88-A(12): 3412-3420 (2005) |
3 | EE | Atsushi Kurokawa,
Masanori Hashimoto,
Akira Kasebe,
Zhangcai Huang,
Yun Yang,
Yasuaki Inoue,
Ryosuke Inagaki,
Hiroo Masuda:
Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance.
IEICE Transactions 88-A(12): 3453-3462 (2005) |
2 | EE | Atsushi Kurokawa,
Toshiki Kanamoto,
Tetsuya Ibe,
Akira Kasebe,
Wei Fong Chang,
Tetsuro Kage,
Yasuaki Inoue,
Hiroo Masuda:
Efficient Dummy Filling Methods to Reduce Interconnect Capacitance and Number of Dummy Metal Fills.
IEICE Transactions 88-A(12): 3471-3478 (2005) |
2004 |
1 | EE | Atsushi Kurokawa,
Nobuto Ono,
Tetsuro Kage,
Hiroo Masuda:
DEPOGIT: dense power-ground interconnect architecture for physical design integrity.
ASP-DAC 2004: 517-522 |