| 2009 |
|---|
| 17 | EE | Jihyun Lee,
Jun-Ki Min,
Chin-Wan Chung:
An effective semantic search technique using ontology.
WWW 2009: 1057-1058 |
| 2008 |
|---|
| 16 | EE | Keunhyung Lee,
Huisoo Lee,
Yongwook Lee,
Jihyun Lee,
Wangrok Oh:
A New Channel Reliability Value for Iterative MAP Turbo Decoder.
WiMob 2008: 333-334 |
| 2007 |
|---|
| 15 | EE | Jihyun Lee,
Danhyung Lee,
Sungwon Kang:
An Overview of the Business Process Maturity Model (BPMM).
APWeb/WAIM Workshops 2007: 384-395 |
| 14 | EE | Sungwon Kang,
Jihyun Lee,
Myungchul Kim,
Woojin Lee:
Towards a Formal Framework for Product Line Test Development.
CIT 2007: 921-926 |
| 13 | EE | Jun-Ki Min,
Jihyun Lee,
Chin-Wan Chung:
An Efficient Encoding and Labeling for Dynamic XML Data.
DASFAA 2007: 715-726 |
| 12 | EE | Myung-Jae Park,
Jihyun Lee,
Chun-Hee Lee,
Jiexi Lin,
Olivier Serres,
Chin-Wan Chung:
An Efficient and Scalable Management of Ontology.
DASFAA 2007: 975-980 |
| 11 | EE | Jihyun Lee,
Hyungyu Park,
Kyungshik Lim:
Rate-Adaptive TCP Spoofing with Segment Aggregation over Asymmetric Long Delay Links.
ICOIN 2007: 123-132 |
| 10 | EE | Youngseok Oh,
Danhyung Lee,
Sungwon Kang,
Jihyun Lee:
Extended Architecture Analysis Description Language for Software Product Line Approach in Embedded Systems.
MEMOCODE 2007: 87-88 |
| 9 | EE | Young-Jun Lee,
Jihyun Lee,
Kyung Ki Kim,
Yong-Bin Kim,
Joseph Ayers:
Low power CMOS electronic central pattern generator design for a biomimetic underwater robot.
Neurocomputing 71(1-3): 284-296 (2007) |
| 2006 |
|---|
| 8 | | Jihyun Lee,
Jin-Hee Cho,
Kyung-Min Park,
Jin-Sam Kim:
Organization of Embedded System Development Methodology for Developing Product Family.
IASTED Conf. on Software Engineering 2006: 154-159 |
| 7 | EE | Jihyun Lee,
Jin-Sam Kim,
Jin-Hee Cho:
A series of development methodologies for a variety of systems in Korea.
ICSE 2006: 612-615 |
| 6 | EE | Daesung Park,
Sungwon Kang,
Jihyun Lee:
Design Phase Analysis of Software Qualities Using Aspect-Oriented Programming.
SNPD 2006: 29-34 |
| 5 | EE | Jihyun Lee,
Yong-Bin Kim:
ASLIC: A low power CMOS analog circuit design automation.
Integration 39(3): 157-181 (2006) |
| 2005 |
|---|
| 4 | EE | Jihyun Lee,
Yong-Bin Kim:
ASLIC: A Low Power CMOS Analog Circuit Design Automation.
ISQED 2005: 470-475 |
| 2004 |
|---|
| 3 | | Young-Jun Lee,
Jihyun Lee,
Yong-Bin Kim,
Joseph Ayers,
A. Volkovskii,
Allen I. Selverston,
Henry D. I. Abarbanel,
Mikhail I. Rabinovich:
Low power real time electronic neuron VLSI design using subthreshold technique.
ISCAS (4) 2004: 744-747 |
| 2003 |
|---|
| 2 | EE | Jihyun Lee,
Jin-Sam Kim,
Gyu-Sang Shin:
Facilitating Reuse of Software Components using Repository Technology.
APSEC 2003: 136- |
| 1 | | Jihyun Lee,
You-Hee Choi,
Gyu-Sang Shin:
A MOF-based Environment to Generate a User-Customizable Case Tool.
SNPD 2003: 146-151 |
