| 2006 |
|---|
| 5 | EE | Jindrich Zejda,
Li Ding:
TBNM - Transistor-Level Boundary Model for Fast Gate-Level Noise Analysis of Macro Blocks.
ISQED 2006: 147-152 |
| 2005 |
|---|
| 4 | EE | Alex Gyure,
Alireza Kasnavi,
Sam C. Lo,
Peivand F. Tehrani,
William Shu,
Mahmoud Shahram,
Joddy W. Wang,
Jindrich Zejda:
Noise Library Characterization for Large Capacity Static Noise Analysis Tools.
ISQED 2005: 28-34 |
| 2004 |
|---|
| 3 | EE | Alireza Kasnavi,
Joddy W. Wang,
Mahmoud Shahram,
Jindrich Zejda:
Analytical modeling of crosstalk noise waveforms using Weibull function.
ICCAD 2004: 141-146 |
| 2002 |
|---|
| 2 | EE | Jindrich Zejda,
Paul Frain:
General framework for removal of clock network pessimism.
ICCAD 2002: 632-639 |
| 1994 |
|---|
| 1 | EE | Jindrich Zejda,
Eduard Cerny:
Gate-level timing verification using waveform narrowing.
EURO-DAC 1994: 374-379 |
