| |
| 2005 | ||
|---|---|---|
| 1 | EE | R. Castagnetti, R. Venkatraman, B. Bartz, C. Monzel, T. Briscoe, Andres Teene, S. Ramesh: A High-Performance SRAM Technology With Reduced Chip-Level Routing Congestion for SoC. ISQED 2005: 193-196 |
| 1 | B. Bartz | [1] |
| 2 | T. Briscoe | [1] |
| 3 | R. Castagnetti | [1] |
| 4 | S. Ramesh (Sethu Ramesh) | [1] |
| 5 | Andres Teene | [1] |
| 6 | R. Venkatraman | [1] |