2005 |
38 | EE | Sreeram Chandrasekar,
Gaurav Kumar Varshney,
V. Visvanathan:
A Comprehensive Methodology for Noise Characterization of ASIC Cell Libraries.
ISQED 2005: 530-535 |
37 | EE | Sreeram Chandrasekar,
V. Visvanathan,
Gaurav Kumar Varshney:
Application of DC Transfer Characteristics in the Elimination of Redundant Vectors for Transient Noise Characterization of Static CMOS Circuits.
VLSI Design 2005: 336-341 |
36 | EE | B. Suresh,
V. Visvanathan,
R. S. Krishnan,
H. S. Jamadagni:
Application of Alpha Power Law Models to PLL Design Methodology.
VLSI Design 2005: 768-773 |
2001 |
35 | EE | Pradip Mandal,
V. Visvanathan:
CMOS op-amp sizing using a geometric programming formulation.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(1): 22-38 (2001) |
2000 |
34 | EE | S. Ramanathan,
S. K. Nandy,
V. Visvanathan:
Reconfigurable Filter Coprocessor Architecture for DSP Applications.
VLSI Signal Processing 26(3): 333-359 (2000) |
1999 |
33 | EE | Avinash K. Gautam,
V. Visvanathan,
S. K. Nandy:
Automatic Generation of Tree Multipliers Using Placement-Driven Netlists.
ICCD 1999: 285-288 |
32 | | Pradip Mandal,
V. Visvanathan:
A New Approach for CMOS Op-Amp Synthesis.
VLSI Design 1999: 189-195 |
31 | EE | S. Ramanathan,
V. Visvanathan,
S. K. Nandy:
Synthesis of Configurable Architectures for DSP Algorithms.
VLSI Design 1999: 350-357 |
30 | EE | S. Ramanathan,
V. Visvanathan:
Low-power pipelined LMS adaptive filter architectures with minimal adaptation delay1.
Integration 27(1): 1-32 (1999) |
29 | EE | S. Ramanathan,
V. Visvanathan,
S. K. Nandy:
Synthesis of ASIPs for DSP algorithms.
Integration 28(1): 13-32 (1999) |
28 | EE | S. Ramanathan,
V. Visvanathan,
S. K. Nandy:
Architectural Synthesis of Computational Engines for Subband Adaptive Filtering.
VLSI Signal Processing 22(3): 173-195 (1999) |
1997 |
27 | EE | S. Ramanathan,
V. Visvanathan:
Low-Power Configurable Processor Array for DLMS Adaptive Filtering.
VLSI Design 1997: 198-207 |
26 | EE | Pradip Mandal,
V. Visvanathan:
A Self-Biased High Performance Folded Cascode CMOS Op-Amp.
VLSI Design 1997: 429-434 |
1996 |
25 | EE | Pradip Mandal,
V. Visvanathan:
Design of high performance two stage CMOS cascode op-amps with stable biasing.
VLSI Design 1996: 234-237 |
24 | EE | S. Ramanathan,
V. Visvanathan:
A systolic architecture for LMS adaptive filtering with minimal adaptation delay.
VLSI Design 1996: 286-289 |
23 | EE | A. Ratan Gupta,
V. Visvanathan:
VLSI Implementation of DSP Architectures.
VLSI Design 1996: 3 |
1995 |
22 | EE | V. Visvanathan,
S. Ramanathan:
A modular systolic architecture for delayed least mean squares adaptive filtering.
VLSI Design 1995: 332-337 |
1994 |
21 | | A. Giri,
V. Visvanathan,
S. K. Nandy,
S. K. Ghoshal:
High Speed Digital Filtering on SRAM-Based FPGAs.
VLSI Design 1994: 229-232 |
20 | | V. K. Anuradha,
V. Visvanathan:
A CORDIC Based Programmable DXT Processor Array.
VLSI Design 1994: 343-348 |
1993 |
19 | EE | Pradip Mandal,
V. Visvanathan:
Macromodeling of the A.C. characteristics of CMOS Op-amps.
ICCAD 1993: 334-340 |
18 | | Kalluri Eswar,
P. Sadayappan,
Chua-Huang Huang,
V. Visvanathan:
Supernodal Sparse Cholesky Facotrization on Distributed-Memory Multiprocessors.
ICPP 1993: 18-22 |
17 | | S. K. Nandy,
Ranjani Narayan,
V. Visvanathan,
P. Sadayappan,
Prashant S. Chauhan:
A Parallel Progressive Refinement Image Rendering Algorithm on a Scalable Multithreaded VLSI Processor Array.
ICPP 1993: 94-97 |
16 | | V. Visvanathan,
Nibedita Mohanty,
S. Ramanathan:
An Area-Efficient Systolic Architecture for Real-Time VLSI Finite Impulse Response Filters.
VLSI Design 1993: 166-171 |
15 | | S. Ramanathan,
Nibedita Mohanty,
V. Visvanathan:
A Methodology for Generating Application Specific Tree Multipliers.
VLSI Design 1993: 176-179 |
14 | | Debabrata Ghosh,
S. K. Nandy,
K. Parthasarathy,
V. Visvanathan:
NPCPL: Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput Designs.
VLSI Design 1993: 341-346 |
13 | | Dinesh Somasekhar,
V. Visvanathan:
A 230MHz Half Bit Level Pipelined Multiplier Using True Single Phase Clocking.
VLSI Design 1993: 347-350 |
12 | EE | Dinesh Somasekhar,
V. Visvanathan:
A 230-MHz half-bit level pipelined multiplier using true single-phase clocking.
IEEE Trans. VLSI Syst. 1(4): 415-422 (1993) |
1991 |
11 | | Kalluri Eswar,
P. Sadayappan,
V. Visvanathan:
Multifrontal Factorization of Sparse Matrices on Shared-Memory Multiprocessors.
ICPP (3) 1991: 159-166 |
1989 |
10 | EE | P. Sadayappan,
V. Visvanathan:
Efficient Sparse Matrix Factorization for Circuit Simulation on Vector Supercomputers.
DAC 1989: 13-18 |
9 | EE | A. P.-C. Ng,
V. Visvanathan:
A Framework for Scheduling Multi-Rate Circuit Simulation.
DAC 1989: 19-24 |
8 | EE | P. Sadayappan,
V. Visvanathan:
Efficient sparse matrix factorization for circuit simulation on vector supercomputers.
IEEE Trans. on CAD of Integrated Circuits and Systems 8(12): 1276-1285 (1989) |
7 | EE | Linda S. Milor,
V. Visvanathan:
Detection of catastrophic faults in analog integrated circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 8(2): 114-130 (1989) |
1988 |
6 | EE | P. Sadayappan,
V. Visvanathan:
Parallelization and performance evaluation of circuit simulation on a shared-memory multiprocessor.
ICS 1988: 254-265 |
5 | | P. Sadayappan,
V. Visvanathan:
Circuit Simulation on Shared-Memory Multiprocessors.
IEEE Trans. Computers 37(12): 1634-1642 (1988) |
1986 |
4 | EE | V. Visvanathan,
Linda S. Milor:
An Efficient Algorithm to Determine the Image of a Parallelepiped Under a Linear Transformation.
Symposium on Computational Geometry 1986: 207-215 |
1984 |
3 | EE | V. Visvanathan,
Alberto L. Sangiovanni-Vincentelli:
A Computational Approach for the Diagnosability of Dynamical Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 3(3): 165-171 (1984) |
1981 |
2 | | V. Visvanathan,
Alberto L. Sangiovanni-Vincentelli:
Diagnosability of Nonlinear Circuits and Systems - Part I: The dc Case.
IEEE Trans. Computers 30(11): 889-898 (1981) |
1 | | Richard Saeks,
Alberto L. Sangiovanni-Vincentelli,
V. Visvanathan:
Diagnosability of Nonlinear Circuits and Systems - Part II: Dynamical Systems.
IEEE Trans. Computers 30(11): 899-904 (1981) |