| |
| 2007 | ||
|---|---|---|
| 5 | EE | Gefu Xu, Adit D. Singh: Delay Test Scan Flip-Flop: DFT for High Coverage Delay Testing. VLSI Design 2007: 763-768 |
| 2006 | ||
| 4 | EE | Gefu Xu, Adit D. Singh: Low Cost Launch-on-Shift Delay Test with Slow Scan Enable. European Test Symposium 2006: 9-14 |
| 3 | EE | Adit D. Singh, Gefu Xu: Output Hazard-Free Transition Tests for Silicon Calibrated Scan Based Delay Testing. VTS 2006: 349-357 |
| 2005 | ||
| 2 | EE | Haihua Yan, Adit D. Singh, Gefu Xu: Delay Defect Characterization Using Low Voltage Test. Asian Test Symposium 2005: 8-13 |
| 1 | EE | Haihua Yan, Gefu Xu, Adit D. Singh: Low Voltage Test in Place of Fast Clock in DDSI Delay Test. ISQED 2005: 316-320 |
| 1 | Adit D. Singh | [1] [2] [3] [4] [5] |
| 2 | Haihua Yan | [1] [2] |