2008 |
18 | EE | Shin-ichi Ohkawa,
Hiroo Masuda,
Yasuaki Inoue:
A Novel Expression of Spatial Correlation by a Random Curved Surface Model and Its Application to LSI Design.
IEICE Transactions 91-A(4): 1062-1070 (2008) |
17 | EE | Masakazu Aoki,
Shin-ichi Ohkawa,
Hiroo Masuda:
Concise Modeling of Transistor Variations in an LSI Chip and Its Application to SRAM Cell Sensitivity Analysis.
IEICE Transactions 91-C(4): 647-654 (2008) |
2006 |
16 | EE | Atsushi Kurokawa,
Akira Kasebe,
Toshiki Kanamoto,
Yun Yang,
Zhangcai Huang,
Yasuaki Inoue,
Hiroo Masuda:
Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills.
IEICE Transactions 89-A(4): 847-855 (2006) |
15 | EE | Atsushi Kurokawa,
Hiroo Masuda,
Junko Fujii,
Toshinori Inoshita,
Akira Kasebe,
Zhangcai Huang,
Yasuaki Inoue:
Determination of Interconnect Structural Parameters for Best- and Worst-Case Delays.
IEICE Transactions 89-A(4): 856-864 (2006) |
2005 |
14 | EE | Hiroo Masuda,
Shin-ichi Ohkawa,
Masakazu Aoki:
Approach for physical design in sub-100 nm era.
ISCAS (6) 2005: 5934-5937 |
13 | EE | Atsushi Kurokawa,
Masaharu Yamamoto,
Nobuto Ono,
Tetsuro Kage,
Yasuaki Inoue,
Hiroo Masuda:
Capacitance and Yield Evaluations Using a 90-nm Process Technology Based on the Dense Power-Ground Interconnect Architecture.
ISQED 2005: 153-158 |
12 | EE | Atsushi Kurokawa,
Toshiki Kanamoto,
Tetsuya Ibe,
Akira Kasebe,
Wei Fong Chang,
Tetsuro Kage,
Yasuaki Inoue,
Hiroo Masuda:
Dummy Filling Methods for Reducing Interconnect Capacitance and Number of Fills.
ISQED 2005: 586-591 |
11 | EE | Atsushi Kurokawa,
Toshiki Kanamoto,
Akira Kasebe,
Yasuaki Inoue,
Hiroo Masuda:
A Practical Approach for Efficiently Extracting Interconnect Capacitances with Floating Dummy Fills.
IEICE Transactions 88-A(11): 3180-3187 (2005) |
10 | EE | Atsushi Kurokawa,
Masanori Hashimoto,
Akira Kasebe,
Zhangcai Huang,
Yun Yang,
Yasuaki Inoue,
Ryosuke Inagaki,
Hiroo Masuda:
Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance.
IEICE Transactions 88-A(12): 3453-3462 (2005) |
9 | EE | Atsushi Kurokawa,
Toshiki Kanamoto,
Tetsuya Ibe,
Akira Kasebe,
Wei Fong Chang,
Tetsuro Kage,
Yasuaki Inoue,
Hiroo Masuda:
Efficient Dummy Filling Methods to Reduce Interconnect Capacitance and Number of Dummy Metal Fills.
IEICE Transactions 88-A(12): 3471-3478 (2005) |
8 | EE | Masakazu Aoki,
Shin-ichi Ohkawa,
Hiroo Masuda:
Design Guidelines and Process Quality Improvement for Treatment of Device Variations in an Lsi Chip.
IEICE Transactions 88-C(5): 788-795 (2005) |
2004 |
7 | EE | Chieki Mizuta,
Jiro Iwai,
Ken Machida,
Tetsuro Kage,
Hiroo Masuda:
Large-scale linear circuit simulation with an inversed inductance matrix.
ASP-DAC 2004: 511-516 |
6 | EE | Atsushi Kurokawa,
Nobuto Ono,
Tetsuro Kage,
Hiroo Masuda:
DEPOGIT: dense power-ground interconnect architecture for physical design integrity.
ASP-DAC 2004: 517-522 |
2003 |
5 | EE | Takashi Sato,
Hiroo Masuda:
Design and Measurement of an Inductance-Oscillator for Analyzing Inductance Impact on On-Chip Interconnect Delay.
ISQED 2003: 395-400 |
1998 |
4 | | Hiroo Masuda,
Katsumi Tsuneno,
Hisako Sato,
Kazutaka Mori:
TCAD/DA for MPU and ASIC Development.
ASP-DAC 1998: 129-134 |
1991 |
3 | EE | Hiroo Masuda,
Jun'ichi Mano,
Ryuichi Ikematsu,
Hitoshi Sugihara,
Yukio Aoki:
A submicrometer MOS transistor I-V model for circuit simulation.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(2): 161-170 (1991) |
1988 |
2 | EE | Hiroo Masuda,
Yukio Aoki,
Jun'ichi Mano,
Osamu Yamashiro:
MOSTSM: a physically based charge conservative MOSFET model.
IEEE Trans. on CAD of Integrated Circuits and Systems 7(12): 1229-1236 (1988) |
1987 |
1 | EE | Yukio Aoki,
Hiroo Masuda,
Shozo Shimada,
Shoji Sato:
A New Design-Centering Methodology for VLSI Device Development.
IEEE Trans. on CAD of Integrated Circuits and Systems 6(3): 452-461 (1987) |