Yinhe Han

2008
19	EE	Lei Zhang, Yinhe Han, Qiang Xu, Xiaowei Li: Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology. DATE 2008: 891-896
2007
18	EE	Yinhe Han, Yu Hu, Xiaowei Li, Huawei Li, Anshuman Chandra: Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit. IEEE Trans. VLSI Syst. 15(5): 531-540 (2007)
17	EE	Wei Wang, Yu Hu, Yinhe Han, Xiaowei Li, You-Sheng Zhang: Leakage Current Optimization Techniques During Test Based on Don't Care Bits Assignment. J. Comput. Sci. Technol. 22(5): 673-680 (2007)
2006
16	EE	Tong Liu, Huawei Li, Xiaowei Li, Yinhe Han: Fast Packet Classification using Group Bit Vector. GLOBECOM 2006
15	EE	Jie Don, Yu Hu, Yinhe Han, Xiaowei Li: An on-chip combinational decompressor for reducing test data volume. ISCAS 2006
14	EE	Yu Hu, Yinhe Han, Xiaowei Li, Huawei Li, Xiaoqing Wen: Compression/Scan Co-design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time. IEICE Transactions 89-D(10): 2616-2625 (2006)
13	EE	Yinhe Han, Huawei Li, Xiaowei Li, Anshuman Chandra: Response compaction for system-on-a-chip based on advanced convolutional codes. Science in China Series F: Information Sciences 49(2): 262-272 (2006)
2005
12	EE	Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li: Theoretic analysis and enhanced X-tolerance of test response compact based on convolutional code. ASP-DAC 2005: 53-58
11	EE	Yinhe Han, Xiaowei Li, Shivakumar Swaminathan, Yu Hu, Anshuman Chandra: Scan Data Volume Reduction Using Periodically Alterable MUXs Decompressor. Asian Test Symposium 2005: 372-377
10	EE	Yanzhuo Tan, Yinhe Han, Xiaowei Li, Feiyin Lu, Yuchuan Chen: Validation analysis and test flow optimization of VLSI chip. ISCAS (6) 2005: 5666-5669
9	EE	Ji Li, Yinhe Han, Xiaowei Li: Deterministic and low power BIST based on scan slice overlapping. ISCAS (6) 2005: 5670-5673
8	EE	Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li: Using MUXs Network to Hide Bunches of Scan Chains. ISQED 2005: 238-243
7	EE	Yinhe Han, Yu Hu, Xiaowei Li, Huawei Li, Anshuman Chandra, Xiaoqing Wen: Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores. IEICE Transactions 88-D(9): 2126-2134 (2005)
6	EE	Yinhe Han, Xiaowei Li, Huawei Li, Anshuman Chandra: Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction. J. Comput. Sci. Technol. 20(2): 201-209 (2005)
2004
5	EE	Yu Hu, Yinhe Han, Huawei Li, Tao Lv, Xiaowei Li: Pair Balance-Based Test Scheduling for SOCs. Asian Test Symposium 2004: 236-241
4	EE	Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li, Anshuman Chandra: Rapid and Energy-Efficient Testing for Embedded Cores. Asian Test Symposium 2004: 8-13
3	EE	Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li, Anshuman Chandra: Response Compaction for Test Time and Test Pins Reduction Based on Advanced Convolutional Codes. DFT 2004: 298-305
2		Yinhe Han, Xiaowei Li: Simultaneous Reduction of Test Data Volume and Testing Power for Scan-Based Test. ESA/VLSI 2004: 374-381
2003
1	EE	Yinhe Han, Yongjun Xu, Huawei Li, Xiaowei Li, Anshuman Chandra: Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Teste. Asian Test Symposium 2003: 440-445

Coauthor Index

1	Anshuman Chandra	[1] [3] [4] [6] [7] [11] [13] [18]
2	Yuchuan Chen	[10]
3	Jie Don	[15]
4	Yu Hu	[3] [4] [5] [7] [8] [11] [12] [14] [15] [17] [18]
5	Huawei Li	[1] [3] [4] [5] [6] [7] [8] [12] [13] [14] [16] [18]
6	Ji Li	[9]
7	Xiaowei Li	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
8	Tong Liu	[16]
9	Feiyin Lu	[10]
10	Tao Lv	[5]
11	Shivakumar Swaminathan	[11]
12	Yanzhuo Tan	[10]
13	Wei Wang	[17]
14	Xiaoqing Wen	[7] [14]
15	Qiang Xu	[19]
16	Yongjun Xu	[1]
17	Lei Zhang	[19]
18	You-Sheng Zhang	[17]