| 1997 |
|---|
| 11 | EE | Mohankumar Guruswamy,
Robert L. Maziasz,
Daniel Dulitz,
Srilata Raman,
Venkat Chiluvuri,
Andrea Fernandez,
Larry G. Jones:
CELLERITY: A Fully Automatic Layout Synthesis System for Standard Cell Libraries.
DAC 1997: 327-332 |
| 10 | EE | Sergey Gavrilov,
Alexey Glebov,
S. Rusakov,
David Blaauw,
Larry G. Jones,
Gopalakrishnan Vijayan:
Fast power loss calculation for digital static CMOS circuits.
ED&TC 1997: 411-415 |
| 1995 |
|---|
| 9 | EE | Alexey Glebov,
David Blaauw,
Larry G. Jones:
Transistor reordering for low power CMOS gates using an SP-BDD representation.
ISLPD 1995: 161-166 |
| 1994 |
|---|
| 8 | EE | Srilata Raman,
C. L. Liu,
Larry G. Jones:
A delay driven FPGA placement algorithm.
EURO-DAC 1994: 277-282 |
| 7 | EE | Larry G. Jones,
David Blaauw:
A cache-based method for accelerating switch-level simulation.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(2): 211-218 (1994) |
| 1992 |
|---|
| 6 | EE | Larry G. Jones:
Zero Delay versus Positive Delay in an Incremental Switch-Level Simulator.
DAC 1992: 424-427 |
| 5 | EE | Larry G. Jones:
An incremental zero/integer delay switch-level simulation environment.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(9): 1131-1139 (1992) |
| 1991 |
|---|
| 4 | EE | Larry G. Jones:
Accelerating Switch-Level Simulation by Function Caching.
DAC 1991: 211-214 |
| 3 | EE | Larry G. Jones:
Fast batch incremental netlist compilation hierarchical schematics.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(7): 922-931 (1991) |
| 1990 |
|---|
| 2 | EE | Larry G. Jones:
Efficient Evaluation of Circular Attribute Grammars.
ACM Trans. Program. Lang. Syst. 12(3): 429-462 (1990) |
| 1986 |
|---|
| 1 | | Larry G. Jones,
Janos Simon:
Hierarchical VLSI Design Systems Based on Attribute Grammars.
POPL 1986: 58-69 |
