| 2007 |
|---|
| 11 | EE | Praveen Tiwari,
Raj S. Mitra,
Manu Chopra,
Alok Jain:
Tutorial T4B: Formal Assertion-Based Verification in Industrial Setting.
VLSI Design 2007: 7 |
| 2006 |
|---|
| 10 | EE | Alok Jain,
Rajiv Saxena,
S. C. Saxena:
An improved and simplified design of cosine-modulated pseudo-QMF filterbanks.
Digital Signal Processing 16(3): 225-232 (2006) |
| 9 | EE | Alok Jain,
Rajiv Saxena,
S. C. Saxena:
Anti-image FIR filters for large interpolation factors.
Signal Processing 86(11): 3240-3245 (2006) |
| 1999 |
|---|
| 8 | EE | Vishnu A. Patankar,
Alok Jain,
Randal E. Bryant:
Formal Verification of an ARM Processor.
VLSI Design 1999: 282-287 |
| 1997 |
|---|
| 7 | | Miroslav N. Velev,
Randal E. Bryant,
Alok Jain:
Efficient Modeling of Memory Arrays in Symbolic Simulation.
CAV 1997: 388-399 |
| 6 | EE | Kyle L. Nelson,
Alok Jain,
Randal E. Bryant:
Formal Verification of a Superscalar Execution Unit.
DAC 1997: 161-166 |
| 1996 |
|---|
| 5 | | Alok Jain,
Kyle L. Nelson,
Randal E. Bryant:
Verifying Nondeterministic Implementations of Deterministic Systems.
FMCAD 1996: 109-125 |
| 1995 |
|---|
| 4 | EE | Samir Jain,
Randal E. Bryant,
Alok Jain:
Automatic Clock Abstraction from Sequential Circuits.
DAC 1995: 707-711 |
| 3 | EE | Manish Pandey,
Alok Jain,
Randal E. Bryant,
Derek L. Beatty,
Gary York,
Samir Jain:
Extraction of finite state machines from transistor netlists by symbolic simulation.
ICCD 1995: 596-601 |
| 1993 |
|---|
| 2 | EE | Alok Jain,
Randal E. Bryant:
Inverter minimization in multi-level logic networks.
ICCAD 1993: 462-465 |
| 1991 |
|---|
| 1 | EE | Alok Jain,
Randal E. Bryant:
Mapping Switch-Level Simulation onto Gate-Level Hardware Accelerators.
DAC 1991: 219-222 |
