Witold A. Pleskacz

2008
19	EE	Artur L. Sobczyk, Arkadiusz W. Luczyk, Witold A. Pleskacz: Controllable Local Clock Signal Generator for Deep Submicron GALS Architectures. DDECS 2008: 14-17
18	EE	Peter Malík, Marcel Baláz, Martin Simlastík, Arkadiusz W. Luczyk, Witold A. Pleskacz: Various MDCT implementations in 0.35µm CMOS. DDECS 2008: 170-173
17	EE	Marcin J. Beresinski, Tomasz Borejko, Witold A. Pleskacz, Viera Stopjaková: Built-In Current Monitor for IDDQ Testing in CMOS 90 nm Technology. DDECS 2008: 259-262
16	EE	Tomasz Borejko, Witold A. Pleskacz: A Resistorless Voltage Reference Source for 90 nm CMOS Technology with Low Sensitivity to Process and Temperature Variations. DDECS 2008: 38-43
2007
15		Artur L. Sobczyk, Arkadiusz W. Luczyk, Witold A. Pleskacz: Power Dissipation in Basic Global Clock Distribution Networks. DDECS 2007: 231-234
14		Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A. Pleskacz, Michal Rakowski: Layout to Logic Defect Analysis for Hierarchical Test Generation. DDECS 2007: 35-40
13		Zbigniew Piatek, Jerzy F. Kolodziejski, Witold A. Pleskacz: ESD Failures of Integrated Circuits and Their Diagnostics Using Transmission Line Pulsing. DDECS 2007: 423-428
2005
12	EE	Joachim Sudbrock, Jaan Raik, Raimund Ubar, Wieslaw Kuzmicz, Witold A. Pleskacz: Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs. DSD 2005: 79-82
2003
11	EE	Dominik Kasprowicz, Witold A. Pleskacz: Improvement of integrated circuit testing reliability by using the defect based approach. Microelectronics Reliability 43(6): 945-953 (2003)
2002
10	EE	Witold A. Pleskacz, Tomasz Borejko, Wieslaw Kuzmicz: CMOS Standard Cells Characterization for IDDQ Testing. DFT 2002: 390-398
9	EE	T. Cibáková, María Fischerová, Elena Gramatová, Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar: Hierarchical test generation for combinational circuits with real defects coverage. Microelectronics Reliability 42(7): 1141-1149 (2002)
2001
8	EE	Witold A. Pleskacz, Dominik Kasprowicz, Tomasz Oleszczak, Wieslaw Kuzmicz: CMOS Standard Cells Characterization for Defect Based Testing. DFT 2001: 384-
7	EE	Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar: Defect-Oriented Fault Simulation and Test Generation in Digital Circuits. ISQED 2001: 365-371
6	EE	Mykola Blyzniuk, Irena Kazymyra, Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar: Probabilistic analysis of CMOS physical defects in VLSI circuits for test coverage improvement. Microelectronics Reliability 41(12): 2023-2040 (2001)
1999
5	EE	Witold A. Pleskacz: Yield Estimation of VLSI Circuits with Downscaled Layouts. DFT 1999: 55-60
4	EE	Witold A. Pleskacz, Charles H. Ouyang, Wojciech Maly: A DRC-based algorithm for extraction of critical areas for opens in large VLSI circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 18(2): 151-162 (1999)
1997
3	EE	Hans T. Heineken, Jitendra Khare, Wojciech Maly, Pranab K. Nag, Charles H. Ouyang, Witold A. Pleskacz: CAD at the Design-Manufacturing Interface. DAC 1997: 321-326
2	EE	Witold A. Pleskacz, Wojciech Maly: Improved Yield Model for Submicron Domain. DFT 1997: 2-10
1	EE	Witold A. Pleskacz, Wojciech Maly, Hans T. Heineken: Detection of Yield Trends. DFT 1997: 62-68

Coauthor Index

1	Marcel Baláz	[18]
2	Marcin J. Beresinski	[17]
3	Mykola Blyzniuk	[6]
4	Tomasz Borejko	[10] [16] [17]
5	T. Cibáková	[9]
6	María Fischerová	[9]
7	Elena Gramatová	[9]
8	Hans T. Heineken	[1] [3]
9	Maksim Jenihhin	[14]
10	Dominik Kasprowicz	[8] [11]
11	Irena Kazymyra	[6]
12	Jitendra Khare	[3]
13	Jerzy F. Kolodziejski	[13]
14	Wieslaw Kuzmicz	[6] [7] [8] [9] [10] [12]
15	Arkadiusz W. Luczyk	[15] [18] [19]
16	Peter Malík	[18]
17	Wojciech Maly	[1] [2] [3] [4]
18	Pranab K. Nag	[3]
19	Tomasz Oleszczak	[8]
20	Charles H. Ouyang	[3] [4]
21	Zbigniew Piatek	[13]
22	Jaan Raik	[6] [7] [9] [12] [14]
23	Michal Rakowski	[14]
24	Martin Simlastík	[18]
25	Artur L. Sobczyk	[15] [19]
26	Viera Stopjaková	[17]
27	Joachim Sudbrock	[12]
28	Raimund Ubar	[6] [7] [9] [12] [14]

Colors in the list of coauthors