| 2003 |
|---|
| 12 | EE | Wai-Ching Douglas Lam,
Cheng-Kok Koh,
Chung-Wen Albert Tsao:
Clock Scheduling for Power Supply Noise Suppression using Genetic Algorithm with Selective Gene Therapy.
ISQED 2003: 327-332 |
| 2002 |
|---|
| 11 | EE | Wai-Ching Douglas Lam,
Cheng-Kok Koh,
Chung-Wen Albert Tsao:
Power Supply Noise Suppression via Clock Skew Scheduling.
ISQED 2002: 355-360 |
| 10 | EE | Chung-Wen Albert Tsao,
Cheng-Kok Koh:
UST/DME: a clock tree router for general skew constraints.
ACM Trans. Design Autom. Electr. Syst. 7(3): 359-379 (2002) |
| 2000 |
|---|
| 9 | | Chung-Wen Albert Tsao,
Cheng-Kok Koh:
UST/DME: A Clock Tree Router for General Skew Constraints.
ICCAD 2000: 400-405 |
| 1998 |
|---|
| 8 | EE | Jason Cong,
Andrew B. Kahng,
Cheng-Kok Koh,
Chung-Wen Albert Tsao:
Bounded-skew clock and Steiner routing.
ACM Trans. Design Autom. Electr. Syst. 3(3): 341-388 (1998) |
| 1997 |
|---|
| 7 | EE | Andrew B. Kahng,
Chung-Wen Albert Tsao:
More Practical Bounded-Skew Clock Routing.
DAC 1997: 594-599 |
| 6 | EE | Andrew B. Kahng,
Chung-Wen Albert Tsao:
Practical Bounded-Skew Clock Routing.
VLSI Signal Processing 16(2-3): 199-215 (1997) |
| 1996 |
|---|
| 5 | EE | Andrew B. Kahng,
Chung-Wen Albert Tsao:
Planar-DME: a single-layer zero-skew clock tree router.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(1): 8-19 (1996) |
| 1995 |
|---|
| 4 | EE | Dennis J.-H. Huang,
Andrew B. Kahng,
Chung-Wen Albert Tsao:
On the Bounded-Skew Clock and Steiner Routing Problems.
DAC 1995: 508-513 |
| 3 | EE | Jason Cong,
Andrew B. Kahng,
Cheng-Kok Koh,
Chung-Wen Albert Tsao:
Bounded-skew clock and Steiner routing under Elmore delay.
ICCAD 1995: 66-71 |
| 1994 |
|---|
| 2 | EE | Chung-Wen Albert Tsao,
Andrew B. Kahng:
Planar-DME: improved planar zero-skew clock routing with minimum pathlength delay.
EURO-DAC 1994: 440-445 |
| 1 | EE | Andrew B. Kahng,
Chung-Wen Albert Tsao:
Low-cost single-layer clock trees with exact zero Elmore delay skew.
ICCAD 1994: 213-218 |
