2006 |
12 | EE | Yibin Ye,
Muhammad M. Khellah,
Dinesh Somasekhar,
Vivek De:
Evaluation of differential vs. single-ended sensing and asymmetric cells in 90 nm logic technology for on-chip caches.
ISCAS 2006 |
2005 |
11 | EE | Muhammad M. Khellah,
Maged Ghoneima,
James Tschanz,
Yibin Ye,
Nasser Kurd,
Javed Barkatullah,
Srikanth Nimmagadda,
Yehea I. Ismail:
A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors.
ICCD 2005: 253-257 |
10 | EE | Yehea I. Ismail,
Muhammad M. Khellah,
Maged Ghoneima,
James Tschanz,
Yibin Ye,
Vivek De:
Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip buses.
ISCAS (1) 2005: 592-595 |
2004 |
9 | EE | Arman Vassighi,
Ali Keshavarzi,
Siva Narendra,
Gerhard Schrom,
Yibin Ye,
Seri Lee,
Greg Chrysler,
Manoj Sachdev,
Vivek De:
Design optimizations for microprocessors at low temperature.
DAC 2004: 2-5 |
2002 |
8 | EE | Tanay Karnik,
Yibin Ye,
James Tschanz,
Liqiong Wei,
Steven M. Burns,
Venkatesh Govindarajulu,
Vivek De,
Shekhar Borkar:
Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors.
DAC 2002: 486-491 |
7 | EE | Fatih Hamzaoglu,
Yibin Ye,
Ali Keshavarzi,
Kevin Zhang,
Siva Narendra,
Shekhar Borkar,
Mircea R. Stan,
Vivek De:
Analysis of dual-VT SRAM cells with full-swing single-ended bit line sensing for on-chip cache.
IEEE Trans. VLSI Syst. 10(2): 91-95 (2002) |
2000 |
6 | EE | Dinesh Somasekhar,
Seung Hoon Choi,
Kaushik Roy,
Yibin Ye,
Vivek De:
Dynamic noise analysis in precharge-evaluate circuits.
DAC 2000: 243 |
1999 |
5 | EE | Yibin Ye,
Kaushik Roy,
Rolf Drechsler:
Power Consumption in XOR-Based Circuits.
ASP-DAC 1999: 299-302 |
4 | EE | Liqiong Wei,
Zhanping Chen,
Kaushik Roy,
Yibin Ye,
Vivek De:
Mixed-Vth (MVT) CMOS Circuit Design Methodology for Low Power Applications.
DAC 1999: 430-435 |
3 | EE | Liqiong Wei,
Zhanping Chen,
Kaushik Roy,
Mark C. Johnson,
Yibin Ye,
Vivek De:
Design and optimization of dual-threshold circuits for low-voltage low-power applications.
IEEE Trans. VLSI Syst. 7(1): 16-24 (1999) |
1997 |
2 | EE | Yibin Ye,
Kaushik Roy:
A Graph-Based Synthesis Algorithm for AND/XOR Networks.
DAC 1997: 107-112 |
1 | EE | Yibin Ye,
Kaushik Roy,
Georgios I. Stamoulis:
Quasi-static energy recovery logic and supply-clock generation circuits.
ISLPED 1997: 96-99 |