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Yibin Ye

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2006
12EEYibin Ye, Muhammad M. Khellah, Dinesh Somasekhar, Vivek De: Evaluation of differential vs. single-ended sensing and asymmetric cells in 90 nm logic technology for on-chip caches. ISCAS 2006
2005
11EEMuhammad M. Khellah, Maged Ghoneima, James Tschanz, Yibin Ye, Nasser Kurd, Javed Barkatullah, Srikanth Nimmagadda, Yehea I. Ismail: A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors. ICCD 2005: 253-257
10EEYehea I. Ismail, Muhammad M. Khellah, Maged Ghoneima, James Tschanz, Yibin Ye, Vivek De: Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip buses. ISCAS (1) 2005: 592-595
2004
9EEArman Vassighi, Ali Keshavarzi, Siva Narendra, Gerhard Schrom, Yibin Ye, Seri Lee, Greg Chrysler, Manoj Sachdev, Vivek De: Design optimizations for microprocessors at low temperature. DAC 2004: 2-5
2002
8EETanay Karnik, Yibin Ye, James Tschanz, Liqiong Wei, Steven M. Burns, Venkatesh Govindarajulu, Vivek De, Shekhar Borkar: Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors. DAC 2002: 486-491
7EEFatih Hamzaoglu, Yibin Ye, Ali Keshavarzi, Kevin Zhang, Siva Narendra, Shekhar Borkar, Mircea R. Stan, Vivek De: Analysis of dual-VT SRAM cells with full-swing single-ended bit line sensing for on-chip cache. IEEE Trans. VLSI Syst. 10(2): 91-95 (2002)
2000
6EEDinesh Somasekhar, Seung Hoon Choi, Kaushik Roy, Yibin Ye, Vivek De: Dynamic noise analysis in precharge-evaluate circuits. DAC 2000: 243
1999
5EEYibin Ye, Kaushik Roy, Rolf Drechsler: Power Consumption in XOR-Based Circuits. ASP-DAC 1999: 299-302
4EELiqiong Wei, Zhanping Chen, Kaushik Roy, Yibin Ye, Vivek De: Mixed-Vth (MVT) CMOS Circuit Design Methodology for Low Power Applications. DAC 1999: 430-435
3EELiqiong Wei, Zhanping Chen, Kaushik Roy, Mark C. Johnson, Yibin Ye, Vivek De: Design and optimization of dual-threshold circuits for low-voltage low-power applications. IEEE Trans. VLSI Syst. 7(1): 16-24 (1999)
1997
2EEYibin Ye, Kaushik Roy: A Graph-Based Synthesis Algorithm for AND/XOR Networks. DAC 1997: 107-112
1EEYibin Ye, Kaushik Roy, Georgios I. Stamoulis: Quasi-static energy recovery logic and supply-clock generation circuits. ISLPED 1997: 96-99

Coauthor Index

1Javed Barkatullah [11]
2Shekhar Y. Borkar (Shekhar Borkar) [7] [8]
3Steven M. Burns [8]
4Zhanping Chen [3] [4]
5Seung Hoon Choi [6]
6Greg Chrysler [9]
7Vivek De [3] [4] [6] [7] [8] [9] [10] [12]
8Rolf Drechsler [5]
9Maged Ghoneima [10] [11]
10Venkatesh Govindarajulu [8]
11Fatih Hamzaoglu [7]
12Yehea I. Ismail [10] [11]
13Mark C. Johnson [3]
14Tanay Karnik [8]
15Ali Keshavarzi [7] [9]
16Muhammad M. Khellah [10] [11] [12]
17Nasser Kurd [11]
18Seri Lee [9]
19Siva Narendra [7] [9]
20Srikanth Nimmagadda [11]
21Kaushik Roy [1] [2] [3] [4] [5] [6]
22Manoj Sachdev [9]
23Gerhard Schrom [9]
24Dinesh Somasekhar [6] [12]
25Georgios I. Stamoulis [1]
26Mircea R. Stan [7]
27James Tschanz [8] [10] [11]
28Arman Vassighi [9]
29Liqiong Wei [3] [4] [8]
30Kevin Zhang [7]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)