1997 | ||
---|---|---|
1 | EE | Rajesh Raina, Robert Bailey, Charles Njinda, Robert F. Molyneaux, Charlie Beh: Efficient Testing of Clock Regenerator Circuits in Scan Designs. DAC 1997: 95-100 |
1 | Robert Bailey | [1] |
2 | Robert F. Molyneaux | [1] |
3 | Charles Njinda | [1] |
4 | Rajesh Raina | [1] |