2009 | ||
---|---|---|
7 | EE | Qiang Wang, Subodh Gupta, Jason Helge Anderson: Clock power reduction for virtex-5 FPGAs. FPGA 2009: 13-22 |
2003 | ||
6 | EE | Subodh Gupta, Farid N. Najm: Energy and peak-current per-cycle estimation at RTL. IEEE Trans. VLSI Syst. 11(4): 525-537 (2003) |
2000 | ||
5 | EE | Subodh Gupta, Farid N. Najm: Power modeling for high-level power estimation. IEEE Trans. VLSI Syst. 8(1): 18-29 (2000) |
4 | EE | Subodh Gupta, Farid N. Najm: Analytical models for RTL power estimation of combinational andsequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 19(7): 808-814 (2000) |
1999 | ||
3 | EE | Subodh Gupta, Farid N. Najm: Power macro-models for DSP blocks with application to high-level synthesis. ISLPED 1999: 103-105 |
2 | EE | Subodh Gupta, Farid N. Najm: Energy-per-cycle estimation at RTL. ISLPED 1999: 121-126 |
1997 | ||
1 | EE | Subodh Gupta, Farid N. Najm: Power Macromodeling for High Level Power Estimation. DAC 1997: 365-370 |
1 | Jason Helge Anderson | [7] |
2 | Farid N. Najm | [1] [2] [3] [4] [5] [6] |
3 | Qiang Wang | [7] |