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Subodh Gupta

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2009
7EEQiang Wang, Subodh Gupta, Jason Helge Anderson: Clock power reduction for virtex-5 FPGAs. FPGA 2009: 13-22
2003
6EESubodh Gupta, Farid N. Najm: Energy and peak-current per-cycle estimation at RTL. IEEE Trans. VLSI Syst. 11(4): 525-537 (2003)
2000
5EESubodh Gupta, Farid N. Najm: Power modeling for high-level power estimation. IEEE Trans. VLSI Syst. 8(1): 18-29 (2000)
4EESubodh Gupta, Farid N. Najm: Analytical models for RTL power estimation of combinational andsequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 19(7): 808-814 (2000)
1999
3EESubodh Gupta, Farid N. Najm: Power macro-models for DSP blocks with application to high-level synthesis. ISLPED 1999: 103-105
2EESubodh Gupta, Farid N. Najm: Energy-per-cycle estimation at RTL. ISLPED 1999: 121-126
1997
1EESubodh Gupta, Farid N. Najm: Power Macromodeling for High Level Power Estimation. DAC 1997: 365-370

Coauthor Index

1Jason Helge Anderson [7]
2Farid N. Najm [1] [2] [3] [4] [5] [6]
3Qiang Wang [7]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)