| 2003 |
|---|
| 6 | EE | Peter Suaris,
Dongsheng Wang,
Pei-Ning Guo,
Nan-Chi Chou:
A physical retiming algorithm for field programmable gate arrays.
FPGA 2003: 247 |
| 2001 |
|---|
| 5 | EE | Pei-Ning Guo,
Toshihiko Takahashi,
Chung-Kuan Cheng,
Takeshi Yoshimura:
Floorplanning using a tree representation.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(2): 281-289 (2001) |
| 1999 |
|---|
| 4 | EE | Pei-Ning Guo,
Chung-Kuan Cheng,
Takeshi Yoshimura:
An O-Tree Representation of Non-Slicing Floorplan and Its Applications.
DAC 1999: 268-273 |
| 3 | EE | Jin Xu,
Pei-Ning Guo,
Chung-Kuan Cheng:
Sequence-pair approach for rectilinear module placement.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(4): 484-493 (1999) |
| 1998 |
|---|
| 2 | EE | Jin Xu,
Pei-Ning Guo,
Chung-Kuan Cheng:
Rectilinear block placement using sequence-pair.
ISPD 1998: 173-178 |
| 1997 |
|---|
| 1 | EE | Jin Xu,
Pei-Ning Guo,
Chung-Kuan Cheng:
Cluster Refinement for Block Placement.
DAC 1997: 762-765 |
