| 1997 |
|---|
| 4 | EE | Jaewon Kim,
Sung-Mo Kang:
An Efficient Transistor Folding Algorithm for Row-Based CMOS Layout Design.
DAC 1997: 456-459 |
| 1996 |
|---|
| 3 | EE | Jaewon Kim,
Sung-Mo Kang:
A new triple-layer OTC channel router.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(9): 1059-1070 (1996) |
| 1995 |
|---|
| 2 | EE | Jaewon Kim,
Sung-Mo Kang:
A timing-driven data path layout synthesis with integer programming.
ICCAD 1995: 716-719 |
| 1994 |
|---|
| 1 | | Jaewon Kim,
Sung-Mo Kang,
Sachin S. Sapatnekar:
High Performance CMOS Macromodule Layout Synthesis.
ISCAS 1994: 179-182 |
