2005 |
21 | | Sam Mitchum,
Robert H. Klenke:
Design and fabrication of a digitally synthesized, digitally controlled ring oscillator.
Circuits, Signals, and Systems 2005: 26-30 |
20 | EE | Robert H. Klenke:
A UAV-Based Computer Engineering Capstone Senior Design Project.
MSE 2005: 111-112 |
2003 |
19 | EE | Robert H. Klenke,
James H. Aylor:
A Proposed Modeling Environment to Teach Performance Modeling and Hardware/Software Codesign to Senior Undergraduates.
MSE 2003: 27-28 |
18 | EE | Jason J. Hein,
James H. Aylor,
Robert H. Klenke:
Performance-Based System Design Education.
MSE 2003: 35-36 |
17 | EE | Robert H. Klenke,
Jerry H. Tucker,
Jason M. Blevins:
A New Hardware/Software Codesign Environment and Senior Capstone Design Project for Computer Engineering.
MSE 2003: 66-67 |
2001 |
16 | EE | Robert H. Klenke:
A Hardware/Software Codesign Senior Capstone Design Project in Computer Engineering.
MSE 2001: 58- |
15 | EE | Robert H. Klenke:
Design of a 32-Bit Microprocessor in an Undergraduate VLSI Design Course.
MSE 2001: 62-63 |
14 | EE | Gang Han,
Robert H. Klenke,
James H. Aylor:
Performance Modeling of Hierarchical Crossbar-Based Multicomputer Systems.
IEEE Trans. Computers 50(9): 877-890 (2001) |
2000 |
13 | EE | Sally A. McKee,
William A. Wulf,
James H. Aylor,
Robert H. Klenke,
Maximo H. Salinas,
Sung I. Hong,
Dee A. B. Weikle:
Dynamic Access Ordering for Streamed Computations.
IEEE Trans. Computers 49(11): 1255-1271 (2000) |
1999 |
12 | EE | Sung I. Hong,
Sally A. McKee,
Maximo H. Salinas,
Robert H. Klenke,
James H. Aylor,
William A. Wulf:
Access Order and Effective Bandwidth for Streams on a Direct Rambus Memory.
HPCA 1999: 80-89 |
11 | EE | Moshe Meyassed,
Robert H. Klenke,
James H. Aylor:
Resolving unknown inputs in mixed-level simulation with sequential elements.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(8): 1151-1164 (1999) |
1998 |
10 | EE | Robert M. McGraw,
James H. Aylor,
Robert H. Klenke:
A Top-Down Design Environment for Developing Pipelined Datapaths.
DAC 1998: 236-241 |
9 | | Sally A. McKee,
Robert H. Klenke,
Kenneth L. Wright,
William A. Wulf,
Maximo H. Salinas,
James H. Aylor,
Alan P. Baston:
Smarter Memory: Improving Bandwidth for Streamed References.
IEEE Computer 31(7): 54-63 (1998) |
1997 |
8 | EE | Robert H. Klenke,
Moshe Meyassed,
James H. Aylor,
Barry W. Johnson,
Ramesh Rao,
Anup Ghosh:
An Integrated Design Environment for Performance and Dependability Analysis.
DAC 1997: 184-189 |
1996 |
7 | EE | Sally A. McKee,
Assaji Aluwihare,
Benjamin H. Clark,
Robert H. Klenke,
Trevor C. Landon,
Christopher W. Oliver,
Maximo H. Salinas,
Adam E. Szymkowiak,
Kenneth L. Wright,
William A. Wulf,
James H. Aylor:
Design and Evaluation of Dynamic Access Ordering Hardware.
International Conference on Supercomputing 1996: 125-132 |
6 | EE | Robert H. Klenke,
James H. Aylor,
Joseph M. Wolf:
An analysis of fault partitioning algorithms for fault partitioned ATPG.
VTS 1996: 231-239 |
5 | EE | Joseph M. Wolf,
Lori M. Kaufman,
Robert H. Klenke,
James H. Aylor,
Ronald Waxman:
An analysis of fault partitioned parallel test generation.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(5): 517-534 (1996) |
1995 |
4 | EE | Robert M. McGraw,
Moshe Meyassed,
Robert H. Klenke,
James H. Aylor,
Ronald D. Williams:
Refinement of system-level designs using hybrid modeling.
ICECCS 1995: 409-416 |
1994 |
3 | | Sally A. McKee,
Robert H. Klenke,
Andrew J. Schwab,
William A. Wulf,
Steven A. Moyer,
James H. Aylor,
Charles Y. Hitchcock:
Experimental Implementation of Dynamic Access Ordering.
HICSS (1) 1994: 431-440 |
1993 |
2 | | Robert H. Klenke,
Lori M. Kaufman,
James H. Aylor,
Ronald Waxman,
Padmini Narayan:
Workstation Based Parallel Test Generation.
ITC 1993: 419-428 |
1992 |
1 | | Robert H. Klenke,
Ronald D. Williams,
James H. Aylor:
Parallel-Processing Techniques for Automatic Test Pattern Generation.
IEEE Computer 25(1): 71-84 (1992) |