| 2001 |
|---|
| 7 | EE | Chau-Shen Chen,
TingTing Hwang,
C. L. Liu:
Architecture driven circuit partitioning.
IEEE Trans. VLSI Syst. 9(2): 383-389 (2001) |
| 1998 |
|---|
| 6 | EE | Chau-Shen Chen,
TingTing Hwang,
C. L. Liu:
Architecture driven circuit partitioning.
ICCAD 1998: 408-411 |
| 5 | EE | Chau-Shen Chen,
TingTing Hwang:
Layout Driven Selection and Chaining of Partial Scan Flip-Flops.
J. Electronic Testing 13(1): 19-27 (1998) |
| 1997 |
|---|
| 4 | EE | Chau-Shen Chen,
TingTing Hwang,
C. L. Liu:
Low Power FPGA Design - A Re-engineering Approach.
DAC 1997: 656-661 |
| 1996 |
|---|
| 3 | EE | Chau-Shen Chen,
Kuang-Hui Lin,
TingTing Hwang:
Layout Driven Selecting and Chaining of Partial Scan.
DAC 1996: 262-267 |
| 1995 |
|---|
| 2 | EE | Chau-Shen Chen,
Yu-Wen Tsay,
TingTing Hwang,
Allen C.-H. Wu,
Youn-Long Lin:
Combining technology mapping and placement for delay-minimization in FPGA designs.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(9): 1076-1084 (1995) |
| 1993 |
|---|
| 1 | EE | Chau-Shen Chen,
Yu-Wen Tsay,
TingTing Hwang,
Allen C.-H. Wu,
Youn-Long Lin:
Combining technology mapping and placement for delay-optimization in FPGA designs.
ICCAD 1993: 123-127 |
