2009 |
36 | EE | Ajit Pal,
Santanu Chattopadhyay:
Synthesis & Testing for Low Power.
VLSI Design 2009: 37-38 |
2008 |
35 | EE | Santanu Kundu,
Santanu Chattopadhyay:
Mesh-of-tree deterministic routing for network-on-chip architecture.
ACM Great Lakes Symposium on VLSI 2008: 343-346 |
34 | EE | Mayur Bubna,
Naresh Shenoy,
Santanu Chattopadhyay:
An efficient greedy approach to PLA folding.
ISCAS 2008: 1356-1359 |
33 | EE | Rafiahamed Shaik,
Mrityunjoy Chakraborty,
Santanu Chattopadhyay:
An efficient finite precision realization of the block adaptive decision feedback equalizer.
ISCAS 2008: 1910-1913 |
32 | EE | Tapas K. Maiti,
Santanu Chattopadhyay:
Don't care filling for power minimization in VLSI circuit testing.
ISCAS 2008: 2637-2640 |
31 | EE | Sambhu Nath Pradhan,
M. Tilak Kumar,
Santanu Chattopadhyay:
Integrated Power-Gating and State Assignment for Low Power FSM Synthesis.
ISVLSI 2008: 269-274 |
2007 |
30 | EE | Chandan Giri,
Dilip Kumar Reddy Tipparthi,
Santanu Chattopadhyay:
Genetic Algorithm Based Approach for Hierarchical SOC Test Scheduling.
ICCTA 2007: 141-145 |
29 | EE | Chandan Giri,
B. Mallikarjuna Rao,
Santanu Chattopadhyay:
Test Data Compression by Spilt-VIHC (SVIHC).
ICCTA 2007: 146-150 |
28 | EE | Chandan Giri,
Soumojit Sarkar,
Santanu Chattopadhyay:
Test Scheduling for Core-Based SOCs Using Genetic Algorithm Based Heuristic Approach.
ICIC (2) 2007: 1032-1041 |
27 | EE | Chandan Giri,
Santanu Chattopadhyay:
Reducing Test-bus Power Consumption in Huffman Coding Based Test Data Compression for SOCs.
ISCAS 2007: 3679-3682 |
26 | EE | Chandan Giri,
Soumojit Sarkar,
Santanu Chattopadhyay:
A genetic algorithm based heuristic technique for power constrained test scheduling in core-based SOCs.
VLSI-SoC 2007: 320-323 |
2005 |
25 | EE | Shantanu Gupta,
Tarang Vaish,
Santanu Chattopadhyay:
Flip-flop chaining architecture for power-efficient scan during test application.
Asian Test Symposium 2005: 410-413 |
24 | EE | Santanu Chattopadhyay,
Manas Kumar Dewangan:
A Combinational Logic Mapper for Actel's SX/AX Family.
VLSI Design 2005: 669-672 |
23 | EE | Santanu Chattopadhyay:
Area Conscious State Assignment with Flip-Flop and Output Polarity Selection for Finite State Machine Synthesis?A Genetic Algorithm Approach.
Comput. J. 48(4): 443-450 (2005) |
2004 |
22 | EE | Batsayan Das,
Dipankar Sarkar,
Santanu Chattopadhyay:
Model checking on state transition diagram.
ASP-DAC 2004: 412-417 |
21 | EE | D. Satyanarayana,
Santanu Chattopadhyay,
Jakki Sasidhar:
Low Power Combinational Circuit Synthesis targeting Multiplexer based FPGAs.
VLSI Design 2004: 79-84 |
2003 |
20 | EE | Santanu Chattopadhyay,
K. Sudarsana Reddy:
Genetic Algorithm based Test Scheduling and Test Access Mechanism Design for System-on-Chips.
VLSI Design 2003: 341-346 |
19 | EE | Santanu Chattopadhyay,
Naveen Choudhary:
Genetic Algorithm based Approach for Low Power Combinational Circuit Testing.
VLSI Design 2003: 552- |
18 | EE | Rohit Pandey,
Santanu Chattopadhyay:
Low Power Technology Mapping for LUT based FPGA "A Genetic Algorithm Approach".
VLSI Design 2003: 79-84 |
2002 |
17 | EE | Santanu Chattopadhyay:
Efficient Circuit Specific Pseudoexhaustive Testing with Cellular Automata.
Asian Test Symposium 2002: 188-193 |
2001 |
16 | EE | Debabrata Bagchi,
Dipanwita Roy Chowdhury,
Joy Mukherjee,
Santanu Chattopadhyay:
A Novel Strategy to Test Core Based Designs.
VLSI Design 2001: 122-127 |
15 | EE | Prabir Dasgupta,
Santanu Chattopadhyay,
Parimal Pal Chaudhuri,
Indranil Sengupta:
Cellular Automata-Based Recursive Pseudoexhaustive Test Pattern Generator.
IEEE Trans. Computers 50(2): 177-185 (2001) |
2000 |
14 | EE | Prabir Dasgupta,
Santanu Chattopadhyay,
Indranil Sengupta:
An ASIC for Cellular Automata Based Message Authentication.
VLSI Design 2000: 538- |
13 | EE | Prabir Dasgupta,
Santanu Chattopadhyay,
Indranil Sengupta:
Cellular Automata Based Deterministic Test Sequence Generator for Sequential Circuits.
VLSI Design 2000: 544-549 |
1998 |
12 | EE | Kolin Paul,
A. Roy,
Prasanta Kumar Nandi,
B. N. Roy,
M. Deb Purkayastha,
Santanu Chattopadhyay,
Parimal Pal Chaudhuri:
Theory and Application of Multiple Attractor Cellular Automata for Fault Diagnosis.
Asian Test Symposium 1998: 388- |
11 | | Santanu Chattopadhyay,
Parimal Pal Chaudhuri:
Genetic Algorithm Based Approach for Integrated State Assignment and Flipflop Selection in Finite State Machine Synthesis.
VLSI Design 1998: 522-527 |
10 | | Santanu Chattopadhyay,
Parimal Pal Chaudhuri:
Efficient Signatures with Linear Space Complexity for Detecting Boolean Function Equivalence.
VLSI Design 1998: 564- |
9 | | Santanu Chattopadhyay,
Dipanwita Roy Chowdhury,
Subarna Bhattacharjee,
Parimal Pal Chaudhuri:
Cellular-Automata-Array-Based Diagnosis of Board Level Faults.
IEEE Trans. Computers 47(8): 817-828 (1998) |
1997 |
8 | EE | Santanu Chattopadhyay,
Parimal Pal Chaudhuri:
Parallel Decoder for Cellular Automata Based Byte Error Correcting Code.
VLSI Design 1997: 527-528 |
7 | EE | Santanu Chattopadhyay,
Samir Roy,
Parimal Pal Chaudhuri:
KGPMIN: an efficient multilevel multioutput AND-OR-XOR minimizer.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(3): 257-265 (1997) |
1996 |
6 | EE | Santanu Chattopadhyay,
S. Mitra,
Parimal Pal Chaudhuri:
Cellular automata based architecture of a database query processor.
VLSI Design 1996: 320-321 |
5 | EE | S. Nandi,
Santanu Chattopadhyay,
Parimal Pal Chaudhuri:
Programmable cellular automata based testbed for fault diagnosis in VLSI circuits.
VLSI Design 1996: 61-64 |
4 | | Santanu Chattopadhyay,
Samir Roy,
Parimal Pal Chaudhuri:
Synthesis of Highly Testable Fixed-Polarity AND-XOR Canonical Networks-A Genetic Algorithm-Based Approach.
IEEE Trans. Computers 45(4): 487-490 (1996) |
3 | | Koppolu Sasidhar,
Santanu Chattopadhyay,
Parimal Pal Chaudhuri:
CAA Decoder for Cellular Automata Based Byte Error Correcting Code.
IEEE Trans. Computers 45(9): 1003-1016 (1996) |
1995 |
2 | EE | Santanu Chattopadhyay,
Dipanwita Roy Chowdhury,
Subarna Bhattacharjee,
Parimal Pal Chaudhuri:
Board level fault diagnosis using cellular automata array.
VLSI Design 1995: 343-348 |
1 | EE | Santanu Chattopadhyay,
Samir Roy,
Parimal Pal Chaudhuri:
Technology mapping on a multi-output logic module built around Cellular Automata Array for a new FPGA architecture.
VLSI Design 1995: 57-62 |