Zainalabedin Navabi

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64EEPejman Lotfi-Kamran, Masoud Daneshtalab, Caro Lucas, Zainalabedin Navabi: BARP-A Dynamic Routing Protocol for Balanced Distribution of Traffic in NoCs. DATE 2008: 1408-1413
63EEMahshid Sedghi, Elnaz Koopahi, Armin Alaghi, Mahmood Fathy, Zainalabedin Navabi: An NoC Test Strategy Based on Flooding with Power, Test Time and Coverage Considerations. VLSI Design 2008: 409-414
62EEPejman Lotfi-Kamran, Mehran Massoumi, Mohammad Mirzaei, Zainalabedin Navabi: Enhanced TED: A New Data Structure for RTL Verification. VLSI Design 2008: 481-486
61EEPejman Lotfi-Kamran, Amir-Mohammad Rahmani, Ali-Asghar Salehpour, Ali Afzali-Kusha, Zainalabedin Navabi: Stall Power Reduction in Pipelined Architecture Processors. VLSI Design 2008: 541-546
60EEMohammad Hosseinabady, Shervin Sharifi, Fabrizio Lombardi, Zainalabedin Navabi: A Selective Trigger Scan Architecture for VLSI Testing. IEEE Trans. Computers 57(3): 316-328 (2008)
59EENaghmeh Karimi, Shahrzad Mirkhani, Zainalabedin Navabi, Fabrizio Lombardi: RT level reliability enhancement by constructing dynamic TMRS. ACM Great Lakes Symposium on VLSI 2007: 172-175
58EEMohammad Hosseinabady, Atefe Dalirsani, Zainalabedin Navabi: Using the inter- and intra-switch regularity in NoC switch testing. DATE 2007: 361-366
57 Mohammad Hossein Neishaburi, Mohammad Reza Kakoee, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi: A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System Services. DDECS 2007: 247-250
56EEArmin Alaghi, Naghmeh Karimi, Mahshid Sedghi, Zainalabedin Navabi: Online NoC Switch Fault Detection and Diagnosis Using a High Level Fault Mode. DFT 2007: 21-30
55EEMohammad Reza Kakoee, Mohammad Hossein Neishaburi, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi: On-Chip Verification of NoCs Using Assertion Processors. DSD 2007: 535-538
54EEParisa Razaghi, Shahrzad Mirkhani, Zainalabedin Navabi: A Configurable Transaction Level Model of a Generic Interconnection Part of Embedded Systems Used in an ESL Design Library. FDL 2007: 171-176
53EENima Honarmand, Hasan Sohofi, Maghsoud Abbaspour, Zainalabedin Navabi: APDL: A Processor Description Language For Design Space Exploration of Embedded Processors. FDL 2007: 50-55
52EEMohammad Hosseinabady, Mohammad Hossein Neishaburi, Zainalabedin Navabi, Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Giorgio Di Natale: Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC. IOLTS 2007: 205-206
51EEAtefe Dalirsani, Mohammad Hosseinabady, Zainalabedin Navabi: An Analytical Model for Reliability Evaluation of NoC Architectures. IOLTS 2007: 49-56
50EEA. Shahabi, Nima Honarmand, Zainalabedin Navabi: Programmable Routing Tables for Degradable Torus-Based Networks on Chips. ISCAS 2007: 1065-1068
49EEMohammad Reza Kakoee, Hamid Shojaei, Hassan Ghasemzadeh, Marjan Sirjani, Zainalabedin Navabi: A New Approach for Design and Verification of Transaction Level Models. ISCAS 2007: 3760-3763
48EEMohammad Hosseinabady, Mohammad Hossein Neishaburi, Pejman Lotfi-Kamran, Zainalabedin Navabi: A UML Based System Level Failure Rate Assessment Technique for SoC Designs. VTS 2007: 243-248
47EENima Honarmand, A. Shahabi, Hasan Sohofi, Maghsoud Abbaspour, Zainalabedin Navabi: High Level Synthesis of Degradable ASICs Using Virtual Binding. VTS 2007: 311-317
46EEMohammad Hosseinabady, Pejman Lotfi-Kamran, Zainalabedin Navabi: Low test application time resource binding for behavioral synthesis. ACM Trans. Design Autom. Electr. Syst. 12(2): (2007)
45EEShervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi: Simultaneous Reduction of Dynamic and Static Power in Scan Structures CoRR abs/0710.4653: (2007)
44EEMasoud Daneshtalab, Ashkan Sobhani, Ali Afzali-Kusha, Omid Fatemi, Zainalabedin Navabi: NoC Hot Spot minimization Using AntNet Dynamic Routing Algorithm. ASAP 2006: 33-38
43EEMohammad Hosseinabady, Abbas Banaiyan, Mahdi Nazm Bojnordi, Zainalabedin Navabi: A concurrent testing method for NoC switches. DATE 2006: 1171-1176
42EEHadi Esmaeilzadeh, A. Moghimi, E. Ebrahimi, Caro Lucas, Zainalabedin Navabi, A. M. Fakhraie: DCim++: a C++ library for object oriented hardware design and distributed simulation. ISCAS 2006
41EEM. Saneei, Ali Afzali-Kusha, Zainalabedin Navabi: Low-power and low-latency cluster topology for local traffic NoCs. ISCAS 2006
40EEMahnaz Sadoughi Yarandi, Armin Alaghi, Zainalabedin Navabi: An Optimized BIST Architecture for FPGA Look-Up Table Testing. ISVLSI 2006: 420-421
39EEMasood Dehyadgari, Mohsen Nickray, Ali Afzali-Kusha, Zainalabedin Navabi: A New Protocol Stack Model for Network on Chip. ISVLSI 2006: 440-441
38EEMohammad D. Mottaghi, Ali Afzali-Kusha, Zainalabedin Navabi: ByZFAD: a low switching activity architecture for shift-and-add multipliers. SBCCI 2006: 179-183
37EEMasoud Daneshtalab, Ali Afzali-Kusha, Ashkan Sobhani, Zainalabedin Navabi, Mohammad D. Mottaghi, Omid Fatemi: Ant colony based routing architecture for minimizing hot spots in NOCs. SBCCI 2006: 56-61
36EEEhsan Atoofian, Zainalabedin Navabi: A Test Approach for Look-Up Table Based FPGAs. J. Comput. Sci. Technol. 21(1): 141-146 (2006)
35EEShervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi: Scan-Based Structure with Reduced Static and Dynamic Power Consumption. J. Low Power Electronics 2(3): 477-487 (2006)
34EEPejman Lotfi-Kamran, Mohammad Hosseinabady, Hamid Shojaei, Mehran Massoumi, Zainalabedin Navabi: TED+: a data structure for microprocessor verification. ASP-DAC 2005: 567-572
33EEHadi Esmaeilzadeh, Saeed Shamshiri, Pooya Saeedi, Zainalabedin Navabi: ISC: Reconfigurable Scan-Cell Architecture for Low Power Testing. Asian Test Symposium 2005: 236-241
32EEShahrzad Mirkhani, Zainalabedin Navabi: Enhancing Fault Simulation Performance by Dynamic Fault Clustering. Asian Test Symposium 2005: 278-283
31EEM. Saneei, Ali Afzali-Kusha, Zainalabedin Navabi: Sign bit reduction encoding for low power applications. DAC 2005: 214-217
30EEShervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi: Simultaneous Reduction of Dynamic and Static Power in Scan Structures. DATE 2005: 846-851
29EEPedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi: Simulating Faults of Combinational IP Core-based SOCs in a PLI Environment. DFT 2005: 389-397
28 Mostafa Naderi, Zainalabedin Navabi: Combination of Assertion and HSAT Methods For Automated Test Vectors Generation. FDL 2005: 479-485
27EEArash Hooshmand, Saeed Shamshiri, Mohammad Alisafaee, Bijan Alizadeh, Pejman Lotfi-Kamran, Mostafa Naderi, Zainalabedin Navabi: Binary Taylor diagrams: an efficient implementation of Taylor expansion diagrams. ISCAS (1) 2005: 424-427
26EEMohammad Alisafaee, Safar Hatami, Ehsan Atoofian, Zainalabedin Navabi, Ali Afzali-Kusha: A low-power scan-path architecture. ISCAS (5) 2005: 5278-5281
25EEHamid Reza Ghasemi, Zainalabedin Navabi: An Effective VHDL-AMS Simulation Algorithm with Event Partitioning. VLSI Design 2005: 762-767
24EESaeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi: Instruction-level test methodology for CPU core self-testing. ACM Trans. Design Autom. Electr. Syst. 10(4): 673-689 (2005)
23EEBijan Alizadeh, Zainalabedin Navabi: Property Checking based on Hierarchical Integer Equations. ACSD 2004: 26-35
22EESaeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi: Test Instruction Set (TIS) for High Level Self-Testing of CPU Cores. Asian Test Symposium 2004: 158-163
21EEBijan Alizadeh, Zainalabedin Navabi: Using Integer Equations to Check PSL Properties in RT Level Design. IWSOC 2004: 83-86
20EEMohammad H. Tehranipour, Seid Mehdi Fakhraie, Zainalabedin Navabi, M. R. Movahedin: A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores. J. Electronic Testing 20(2): 155-168 (2004)
19EEZainalabedin Navabi, Shahrzad Mirkhani, Meisam Lavasani, Fabrizio Lombardi: Using RT Level Component Descriptions for Single Stuck-at Hierarchical Fault Simulation. J. Electronic Testing 20(6): 575-589 (2004)
18EEPedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi: The VPI-Based Combinational IP Core Module-Based Mixed Level Serial Fault Simulation and Test Generation Methodology. Asian Test Symposium 2003: 274-277
17EEEhsan Atoofian, Zainalabedin Navabi: A BIST Architecture for FPGA Look-Up Table Testing Reduces Reconfigurations. Asian Test Symposium 2003: 84-89
16EEShervin Sharifi, Mohammad Hosseinabady, Pedram A. Riahi, Zainalabedin Navabi: Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture. DFT 2003: 352-360
15 Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi: Using Verilog VPI for Mixed Level Serial Fault Simulation in a Test Generation Environment. Embedded Systems and Applications 2003: 139-143
14EEElham Safi, Zohreh Karimi, Maghsoud Abbaspour, Zainalabedin Navabi: Utilizing Various ADL Facets for Instruction Level CPU Test. MTV 2003: 38-
13 Morteza Fayyazi, David R. Kaeli, Zainalabedin Navabi: Dynamic Input Buffer Allocation (DIBA) for Fault Tolerant Ethernet Packet Switching. PDPTA 2003: 819-823
12 Elham Safi, Reihaneh Saberi, Zohreh Karimi, Zainalabedin Navabi: Processor Testing Using an ADL Description and Genetic Algorithms. VLSI-SOC 2003: 186-
11 Shervin Sharifi, Mohammad Hosseinabady, Zainalabedin Navabi: Selective Trigger Scan Architecture for Reducing Power, Time and Data Volume in SoC Testing. VLSI-SOC 2003: 215-220
10 Ehsan Atoofian, Zainalabedin Navabi: A Low Power BIST Architecture for FPGA Look-Up Table Testing. VLSI-SOC 2003: 394-397
9EEShahrzad Mirkhani, Meisam Lavasani, Zainalabedin Navabi: Hierarchical Fault Simulation Using Behavioral and Gate Level Hardware Models. Asian Test Symposium 2002: 374-
8EEFarzin Karimi, Waleed Meleis, Zainalabedin Navabi, Fabrizio Lombardi: Data Compression for System-on-Chip Testing Using ATE. DFT 2002: 166-176
7EEHamed Farshbaf, Mina Zolfy, Shahrzad Mirkhani, Zainalabedin Navabi: Fault Simulation for VHDL Based Test Bench and BIST Evaluation. Asian Test Symposium 2001: 396-
6EEMina Zolfy, Shahrzad Mirkhani, Zainalabedin Navabi: Adaptation of an event-driven simulation environment to sequentially propagated concurrent fault simulation. DATE 2001: 823
5EEMohammad H. Tehranipour, Zainalabedin Navabi, Seid Mehdi Fakhraie: An efficient BIST method for testing of embedded SRAMs. ISCAS (5) 2001: 73-76
4 Zainalabedin Navabi, Amirhooshang Hashemi, Massoud Eghtesad, Mankuan Michael Vai: Modeling Timing Behavior of Logic Circuits Using Piecewise Linear Models. CHDL 1993: 569-586
3EEZainalabedin Navabi: A high-level language for design and modeling of hardware. Journal of Systems and Software 18(1): 5-18 (1992)
2EEF. J. Hill, Zainalabedin Navabi, C. H. Chiang, Duan-Ping Chen, M. Masud: Hardware Compilation from an RTL to a Storage Logic Array Target. IEEE Trans. on CAD of Integrated Circuits and Systems 3(3): 208-217 (1984)
1 F. J. Hill, R. E. Swanson, M. Masud, Zainalabedin Navabi: Structure Specification with a Procedural Hardware Description Language. IEEE Trans. Computers 30(2): 157-161 (1981)

Coauthor Index

1Maghsoud Abbaspour [14] [47] [53]
2Ali Afzali-Kusha [26] [30] [31] [35] [37] [38] [39] [41] [44] [45] [61]
3Armin Alaghi [40] [56] [63]
4Mohammad Alisafaee [26] [27]
5Bijan Alizadeh [21] [23] [27]
6Ehsan Atoofian [10] [17] [26] [36]
7Abbas Banaiyan [43]
8Alfredo Benso [52]
9Mahdi Nazm Bojnordi [43]
10Stefano Di Carlo [52]
11Duan-Ping Chen [2]
12C. H. Chiang [2]
13Atefe Dalirsani [51] [58]
14Masoud Daneshtalab [37] [44] [55] [57] [64]
15Masood Dehyadgari [39]
16E. Ebrahimi [42]
17Massoud Eghtesad [4]
18Hadi Esmaeilzadeh [22] [24] [33] [42]
19A. M. Fakhraie [42]
20Seid Mehdi Fakhraie [5] [20]
21Hamed Farshbaf [7]
22Omid Fatemi [37] [44]
23Mahmood Fathy [63]
24Morteza Fayyazi [13]
25Hamid Reza Ghasemi [25]
26Hassan Ghasemzadeh [49]
27Amirhooshang Hashemi [4]
28Safar Hatami [26]
29F. J. Hill [1] [2]
30Nima Honarmand [47] [50] [53]
31Arash Hooshmand [27]
32Mohammad Hosseinabady [11] [16] [30] [34] [35] [43] [45] [46] [48] [51] [52] [58] [60]
33Javid Jaffari [30] [35] [45]
34David R. Kaeli [13]
35Mohammad Reza Kakoee [49] [55] [57]
36Farzin Karimi [8]
37Naghmeh Karimi [56] [59]
38Zohreh Karimi [12] [14]
39Elnaz Koopahi [63]
40Meisam Lavasani [9] [19]
41Fabrizio Lombardi [8] [15] [18] [19] [29] [59] [60]
42Pejman Lotfi-Kamran [27] [34] [46] [48] [61] [62] [64]
43Caro Lucas [42] [64]
44Mehran Massoumi [34] [62]
45M. Masud [1] [2]
46Waleed Meleis [8]
47Shahrzad Mirkhani [6] [7] [9] [19] [32] [54] [59]
48Mohammad Mirzaei [62]
49A. Moghimi [42]
50Mohammad D. Mottaghi [37] [38]
51M. R. Movahedin [20]
52Mostafa Naderi [27] [28]
53Giorgio Di Natale [52]
54Mohammad Hossein Neishaburi [48] [52] [55] [57]
55Mohsen Nickray [39]
56Paolo Prinetto [52]
57Amir-Mohammad Rahmani [61]
58Parisa Razaghi [54]
59Pedram A. Riahi [15] [16] [18] [29]
60Reihaneh Saberi [12]
61Pooya Saeedi [33]
62Saeed Safari [55] [57]
63Elham Safi [12] [14]
64Ali-Asghar Salehpour [61]
65M. Saneei [31] [41]
66Mahshid Sedghi [56] [63]
67A. Shahabi [47] [50]
68Saeed Shamshiri [22] [24] [27] [33]
69Shervin Sharifi [11] [16] [30] [35] [45] [60]
70Hamid Shojaei [34] [49]
71Marjan Sirjani [49]
72Ashkan Sobhani [37] [44]
73Hasan Sohofi [47] [53]
74R. E. Swanson [1]
75Mohammad H. Tehranipour [5] [20]
76Mankuan Michael Vai [4]
77Mahnaz Sadoughi Yarandi [40]
78Mina Zolfy [6] [7]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)