| 2008 |
|---|
| 64 | EE | Pejman Lotfi-Kamran,
Masoud Daneshtalab,
Caro Lucas,
Zainalabedin Navabi:
BARP-A Dynamic Routing Protocol for Balanced Distribution of Traffic in NoCs.
DATE 2008: 1408-1413 |
| 63 | EE | Mahshid Sedghi,
Elnaz Koopahi,
Armin Alaghi,
Mahmood Fathy,
Zainalabedin Navabi:
An NoC Test Strategy Based on Flooding with Power, Test Time and Coverage Considerations.
VLSI Design 2008: 409-414 |
| 62 | EE | Pejman Lotfi-Kamran,
Mehran Massoumi,
Mohammad Mirzaei,
Zainalabedin Navabi:
Enhanced TED: A New Data Structure for RTL Verification.
VLSI Design 2008: 481-486 |
| 61 | EE | Pejman Lotfi-Kamran,
Amir-Mohammad Rahmani,
Ali-Asghar Salehpour,
Ali Afzali-Kusha,
Zainalabedin Navabi:
Stall Power Reduction in Pipelined Architecture Processors.
VLSI Design 2008: 541-546 |
| 60 | EE | Mohammad Hosseinabady,
Shervin Sharifi,
Fabrizio Lombardi,
Zainalabedin Navabi:
A Selective Trigger Scan Architecture for VLSI Testing.
IEEE Trans. Computers 57(3): 316-328 (2008) |
| 2007 |
|---|
| 59 | EE | Naghmeh Karimi,
Shahrzad Mirkhani,
Zainalabedin Navabi,
Fabrizio Lombardi:
RT level reliability enhancement by constructing dynamic TMRS.
ACM Great Lakes Symposium on VLSI 2007: 172-175 |
| 58 | EE | Mohammad Hosseinabady,
Atefe Dalirsani,
Zainalabedin Navabi:
Using the inter- and intra-switch regularity in NoC switch testing.
DATE 2007: 361-366 |
| 57 | | Mohammad Hossein Neishaburi,
Mohammad Reza Kakoee,
Masoud Daneshtalab,
Saeed Safari,
Zainalabedin Navabi:
A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System Services.
DDECS 2007: 247-250 |
| 56 | EE | Armin Alaghi,
Naghmeh Karimi,
Mahshid Sedghi,
Zainalabedin Navabi:
Online NoC Switch Fault Detection and Diagnosis Using a High Level Fault Mode.
DFT 2007: 21-30 |
| 55 | EE | Mohammad Reza Kakoee,
Mohammad Hossein Neishaburi,
Masoud Daneshtalab,
Saeed Safari,
Zainalabedin Navabi:
On-Chip Verification of NoCs Using Assertion Processors.
DSD 2007: 535-538 |
| 54 | EE | Parisa Razaghi,
Shahrzad Mirkhani,
Zainalabedin Navabi:
A Configurable Transaction Level Model of a Generic Interconnection Part of Embedded Systems Used in an ESL Design Library.
FDL 2007: 171-176 |
| 53 | EE | Nima Honarmand,
Hasan Sohofi,
Maghsoud Abbaspour,
Zainalabedin Navabi:
APDL: A Processor Description Language For Design Space Exploration of Embedded Processors.
FDL 2007: 50-55 |
| 52 | EE | Mohammad Hosseinabady,
Mohammad Hossein Neishaburi,
Zainalabedin Navabi,
Alfredo Benso,
Stefano Di Carlo,
Paolo Prinetto,
Giorgio Di Natale:
Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC.
IOLTS 2007: 205-206 |
| 51 | EE | Atefe Dalirsani,
Mohammad Hosseinabady,
Zainalabedin Navabi:
An Analytical Model for Reliability Evaluation of NoC Architectures.
IOLTS 2007: 49-56 |
| 50 | EE | A. Shahabi,
Nima Honarmand,
Zainalabedin Navabi:
Programmable Routing Tables for Degradable Torus-Based Networks on Chips.
ISCAS 2007: 1065-1068 |
| 49 | EE | Mohammad Reza Kakoee,
Hamid Shojaei,
Hassan Ghasemzadeh,
Marjan Sirjani,
Zainalabedin Navabi:
A New Approach for Design and Verification of Transaction Level Models.
ISCAS 2007: 3760-3763 |
| 48 | EE | Mohammad Hosseinabady,
Mohammad Hossein Neishaburi,
Pejman Lotfi-Kamran,
Zainalabedin Navabi:
A UML Based System Level Failure Rate Assessment Technique for SoC Designs.
VTS 2007: 243-248 |
| 47 | EE | Nima Honarmand,
A. Shahabi,
Hasan Sohofi,
Maghsoud Abbaspour,
Zainalabedin Navabi:
High Level Synthesis of Degradable ASICs Using Virtual Binding.
VTS 2007: 311-317 |
| 46 | EE | Mohammad Hosseinabady,
Pejman Lotfi-Kamran,
Zainalabedin Navabi:
Low test application time resource binding for behavioral synthesis.
ACM Trans. Design Autom. Electr. Syst. 12(2): (2007) |
| 45 | EE | Shervin Sharifi,
Javid Jaffari,
Mohammad Hosseinabady,
Ali Afzali-Kusha,
Zainalabedin Navabi:
Simultaneous Reduction of Dynamic and Static Power in Scan Structures
CoRR abs/0710.4653: (2007) |
| 2006 |
|---|
| 44 | EE | Masoud Daneshtalab,
Ashkan Sobhani,
Ali Afzali-Kusha,
Omid Fatemi,
Zainalabedin Navabi:
NoC Hot Spot minimization Using AntNet Dynamic Routing Algorithm.
ASAP 2006: 33-38 |
| 43 | EE | Mohammad Hosseinabady,
Abbas Banaiyan,
Mahdi Nazm Bojnordi,
Zainalabedin Navabi:
A concurrent testing method for NoC switches.
DATE 2006: 1171-1176 |
| 42 | EE | Hadi Esmaeilzadeh,
A. Moghimi,
E. Ebrahimi,
Caro Lucas,
Zainalabedin Navabi,
A. M. Fakhraie:
DCim++: a C++ library for object oriented hardware design and distributed simulation.
ISCAS 2006 |
| 41 | EE | M. Saneei,
Ali Afzali-Kusha,
Zainalabedin Navabi:
Low-power and low-latency cluster topology for local traffic NoCs.
ISCAS 2006 |
| 40 | EE | Mahnaz Sadoughi Yarandi,
Armin Alaghi,
Zainalabedin Navabi:
An Optimized BIST Architecture for FPGA Look-Up Table Testing.
ISVLSI 2006: 420-421 |
| 39 | EE | Masood Dehyadgari,
Mohsen Nickray,
Ali Afzali-Kusha,
Zainalabedin Navabi:
A New Protocol Stack Model for Network on Chip.
ISVLSI 2006: 440-441 |
| 38 | EE | Mohammad D. Mottaghi,
Ali Afzali-Kusha,
Zainalabedin Navabi:
ByZFAD: a low switching activity architecture for shift-and-add multipliers.
SBCCI 2006: 179-183 |
| 37 | EE | Masoud Daneshtalab,
Ali Afzali-Kusha,
Ashkan Sobhani,
Zainalabedin Navabi,
Mohammad D. Mottaghi,
Omid Fatemi:
Ant colony based routing architecture for minimizing hot spots in NOCs.
SBCCI 2006: 56-61 |
| 36 | EE | Ehsan Atoofian,
Zainalabedin Navabi:
A Test Approach for Look-Up Table Based FPGAs.
J. Comput. Sci. Technol. 21(1): 141-146 (2006) |
| 35 | EE | Shervin Sharifi,
Javid Jaffari,
Mohammad Hosseinabady,
Ali Afzali-Kusha,
Zainalabedin Navabi:
Scan-Based Structure with Reduced Static and Dynamic Power Consumption.
J. Low Power Electronics 2(3): 477-487 (2006) |
| 2005 |
|---|
| 34 | EE | Pejman Lotfi-Kamran,
Mohammad Hosseinabady,
Hamid Shojaei,
Mehran Massoumi,
Zainalabedin Navabi:
TED+: a data structure for microprocessor verification.
ASP-DAC 2005: 567-572 |
| 33 | EE | Hadi Esmaeilzadeh,
Saeed Shamshiri,
Pooya Saeedi,
Zainalabedin Navabi:
ISC: Reconfigurable Scan-Cell Architecture for Low Power Testing.
Asian Test Symposium 2005: 236-241 |
| 32 | EE | Shahrzad Mirkhani,
Zainalabedin Navabi:
Enhancing Fault Simulation Performance by Dynamic Fault Clustering.
Asian Test Symposium 2005: 278-283 |
| 31 | EE | M. Saneei,
Ali Afzali-Kusha,
Zainalabedin Navabi:
Sign bit reduction encoding for low power applications.
DAC 2005: 214-217 |
| 30 | EE | Shervin Sharifi,
Javid Jaffari,
Mohammad Hosseinabady,
Ali Afzali-Kusha,
Zainalabedin Navabi:
Simultaneous Reduction of Dynamic and Static Power in Scan Structures.
DATE 2005: 846-851 |
| 29 | EE | Pedram A. Riahi,
Zainalabedin Navabi,
Fabrizio Lombardi:
Simulating Faults of Combinational IP Core-based SOCs in a PLI Environment.
DFT 2005: 389-397 |
| 28 | | Mostafa Naderi,
Zainalabedin Navabi:
Combination of Assertion and HSAT Methods For Automated Test Vectors Generation.
FDL 2005: 479-485 |
| 27 | EE | Arash Hooshmand,
Saeed Shamshiri,
Mohammad Alisafaee,
Bijan Alizadeh,
Pejman Lotfi-Kamran,
Mostafa Naderi,
Zainalabedin Navabi:
Binary Taylor diagrams: an efficient implementation of Taylor expansion diagrams.
ISCAS (1) 2005: 424-427 |
| 26 | EE | Mohammad Alisafaee,
Safar Hatami,
Ehsan Atoofian,
Zainalabedin Navabi,
Ali Afzali-Kusha:
A low-power scan-path architecture.
ISCAS (5) 2005: 5278-5281 |
| 25 | EE | Hamid Reza Ghasemi,
Zainalabedin Navabi:
An Effective VHDL-AMS Simulation Algorithm with Event Partitioning.
VLSI Design 2005: 762-767 |
| 24 | EE | Saeed Shamshiri,
Hadi Esmaeilzadeh,
Zainalabedin Navabi:
Instruction-level test methodology for CPU core self-testing.
ACM Trans. Design Autom. Electr. Syst. 10(4): 673-689 (2005) |
| 2004 |
|---|
| 23 | EE | Bijan Alizadeh,
Zainalabedin Navabi:
Property Checking based on Hierarchical Integer Equations.
ACSD 2004: 26-35 |
| 22 | EE | Saeed Shamshiri,
Hadi Esmaeilzadeh,
Zainalabedin Navabi:
Test Instruction Set (TIS) for High Level Self-Testing of CPU Cores.
Asian Test Symposium 2004: 158-163 |
| 21 | EE | Bijan Alizadeh,
Zainalabedin Navabi:
Using Integer Equations to Check PSL Properties in RT Level Design.
IWSOC 2004: 83-86 |
| 20 | EE | Mohammad H. Tehranipour,
Seid Mehdi Fakhraie,
Zainalabedin Navabi,
M. R. Movahedin:
A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores.
J. Electronic Testing 20(2): 155-168 (2004) |
| 19 | EE | Zainalabedin Navabi,
Shahrzad Mirkhani,
Meisam Lavasani,
Fabrizio Lombardi:
Using RT Level Component Descriptions for Single Stuck-at Hierarchical Fault Simulation.
J. Electronic Testing 20(6): 575-589 (2004) |
| 2003 |
|---|
| 18 | EE | Pedram A. Riahi,
Zainalabedin Navabi,
Fabrizio Lombardi:
The VPI-Based Combinational IP Core Module-Based Mixed Level Serial Fault Simulation and Test Generation Methodology.
Asian Test Symposium 2003: 274-277 |
| 17 | EE | Ehsan Atoofian,
Zainalabedin Navabi:
A BIST Architecture for FPGA Look-Up Table Testing Reduces Reconfigurations.
Asian Test Symposium 2003: 84-89 |
| 16 | EE | Shervin Sharifi,
Mohammad Hosseinabady,
Pedram A. Riahi,
Zainalabedin Navabi:
Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture.
DFT 2003: 352-360 |
| 15 | | Pedram A. Riahi,
Zainalabedin Navabi,
Fabrizio Lombardi:
Using Verilog VPI for Mixed Level Serial Fault Simulation in a Test Generation Environment.
Embedded Systems and Applications 2003: 139-143 |
| 14 | EE | Elham Safi,
Zohreh Karimi,
Maghsoud Abbaspour,
Zainalabedin Navabi:
Utilizing Various ADL Facets for Instruction Level CPU Test.
MTV 2003: 38- |
| 13 | | Morteza Fayyazi,
David R. Kaeli,
Zainalabedin Navabi:
Dynamic Input Buffer Allocation (DIBA) for Fault Tolerant Ethernet Packet Switching.
PDPTA 2003: 819-823 |
| 12 | | Elham Safi,
Reihaneh Saberi,
Zohreh Karimi,
Zainalabedin Navabi:
Processor Testing Using an ADL Description and Genetic Algorithms.
VLSI-SOC 2003: 186- |
| 11 | | Shervin Sharifi,
Mohammad Hosseinabady,
Zainalabedin Navabi:
Selective Trigger Scan Architecture for Reducing Power, Time and Data Volume in SoC Testing.
VLSI-SOC 2003: 215-220 |
| 10 | | Ehsan Atoofian,
Zainalabedin Navabi:
A Low Power BIST Architecture for FPGA Look-Up Table Testing.
VLSI-SOC 2003: 394-397 |
| 2002 |
|---|
| 9 | EE | Shahrzad Mirkhani,
Meisam Lavasani,
Zainalabedin Navabi:
Hierarchical Fault Simulation Using Behavioral and Gate Level Hardware Models.
Asian Test Symposium 2002: 374- |
| 8 | EE | Farzin Karimi,
Waleed Meleis,
Zainalabedin Navabi,
Fabrizio Lombardi:
Data Compression for System-on-Chip Testing Using ATE.
DFT 2002: 166-176 |
| 2001 |
|---|
| 7 | EE | Hamed Farshbaf,
Mina Zolfy,
Shahrzad Mirkhani,
Zainalabedin Navabi:
Fault Simulation for VHDL Based Test Bench and BIST Evaluation.
Asian Test Symposium 2001: 396- |
| 6 | EE | Mina Zolfy,
Shahrzad Mirkhani,
Zainalabedin Navabi:
Adaptation of an event-driven simulation environment to sequentially propagated concurrent fault simulation.
DATE 2001: 823 |
| 5 | EE | Mohammad H. Tehranipour,
Zainalabedin Navabi,
Seid Mehdi Fakhraie:
An efficient BIST method for testing of embedded SRAMs.
ISCAS (5) 2001: 73-76 |
| 1993 |
|---|
| 4 | | Zainalabedin Navabi,
Amirhooshang Hashemi,
Massoud Eghtesad,
Mankuan Michael Vai:
Modeling Timing Behavior of Logic Circuits Using Piecewise Linear Models.
CHDL 1993: 569-586 |
| 1992 |
|---|
| 3 | EE | Zainalabedin Navabi:
A high-level language for design and modeling of hardware.
Journal of Systems and Software 18(1): 5-18 (1992) |
| 1984 |
|---|
| 2 | EE | F. J. Hill,
Zainalabedin Navabi,
C. H. Chiang,
Duan-Ping Chen,
M. Masud:
Hardware Compilation from an RTL to a Storage Logic Array Target.
IEEE Trans. on CAD of Integrated Circuits and Systems 3(3): 208-217 (1984) |
| 1981 |
|---|
| 1 | | F. J. Hill,
R. E. Swanson,
M. Masud,
Zainalabedin Navabi:
Structure Specification with a Procedural Hardware Description Language.
IEEE Trans. Computers 30(2): 157-161 (1981) |
