| 2007 |
|---|
| 10 | EE | Yoshiyuki Nakamura,
Thomas Clouqueur,
Kewal K. Saluja,
Hideo Fujiwara:
Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester.
IEEE Trans. VLSI Syst. 15(7): 790-800 (2007) |
| 9 | EE | Chia Yee Ooi,
Thomas Clouqueur,
Hideo Fujiwara:
Analysis of Test Generation Complexity for Stuck-At and Path Delay Faults Based on tauk-Notation.
IEICE Transactions 90-D(8): 1202-1212 (2007) |
| 2006 |
|---|
| 8 | EE | Yoshiyuki Nakamura,
Thomas Clouqueur,
Kewal K. Saluja,
Hideo Fujiwara:
Error Identification in At-Speed Scan BIST Environment in the Presence of Circuit and Tester Speed Mismatch.
IEICE Transactions 89-D(3): 1165-1172 (2006) |
| 7 | EE | Tai-Lin Chin,
Thomas Clouqueur,
Parameswaran Ramanathan,
Kewal K. Saluja:
Vulnerability of Surveillance Networks to Faults.
IJDSN 2(3): 289-311 (2006) |
| 2005 |
|---|
| 6 | EE | Thomas Clouqueur,
Hideo Fujiwara,
Kewal K. Saluja:
A Class of Linear Space Compactors for Enhanced Diagnostic.
Asian Test Symposium 2005: 260-265 |
| 5 | EE | Chia Yee Ooi,
Thomas Clouqueur,
Hideo Fujiwara:
Classification of Sequential Circuits Based on tauk Notation and Its Applications.
IEICE Transactions 88-D(12): 2738-2747 (2005) |
| 2004 |
|---|
| 4 | EE | Thomas Clouqueur,
Kewal K. Saluja,
Parameswaran Ramanathan:
Fault Tolerance in Collaborative Sensor Networks for Target Detection.
IEEE Trans. Computers 53(3): 320-333 (2004) |
| 2003 |
|---|
| 3 | EE | Thomas Clouqueur,
Veradej Phipatanasuphorn,
Parameswaran Ramanathan,
Kewal K. Saluja:
Sensor Deployment Strategy for Detection of Targets Traversing a Region.
MONET 8(4): 453-461 (2003) |
| 2002 |
|---|
| 2 | EE | Thomas Clouqueur,
Veradej Phipatanasuphorn,
Parameswaran Ramanathan,
Kewal K. Saluja:
Sensor deployment strategy for target detection.
WSNA 2002: 42-48 |
| 2001 |
|---|
| 1 | EE | Thomas Clouqueur,
Ozen Ercevik,
Kewal K. Saluja,
Hiroshi Takahashi:
Efficient Signature-Based Fault Diagnosis Using Variable Size Windows.
VLSI Design 2001: 391-396 |
