| 2007 |
|---|
| 9 | EE | V. R. Devanathan,
C. P. Ravikumar,
V. Kamakoti:
Interactive presentation: On power-profiling and pattern generation for power-safe scan tests.
DATE 2007: 534-539 |
| 8 | EE | Srivaths Ravi,
V. R. Devanathan,
Rubin A. Parekhji:
Methodology for low power test pattern generation using activity threshold control logic.
ICCAD 2007: 526-529 |
| 7 | EE | V. R. Devanathan,
C. P. Ravikumar,
V. Kamakoti:
Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms.
VLSI Design 2007: 351-356 |
| 6 | EE | V. R. Devanathan,
C. P. Ravikumar,
V. Kamakoti:
Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test.
VTS 2007: 167-172 |
| 5 | EE | V. R. Devanathan,
C. P. Ravikumar,
V. Kamakoti:
Variation-Tolerant, Power-Safe Pattern Generation.
IEEE Design & Test of Computers 24(4): 374-384 (2007) |
| 2006 |
|---|
| 4 | EE | V. R. Devanathan,
C. P. Ravikumar,
V. Kamakoti:
On Reducing Peak Capture Power of Transition Delay Fault Test for SoCs with Unwrapped Cores.
J. Low Power Electronics 2(3): 464-476 (2006) |
| 2005 |
|---|
| 3 | EE | V. R. Devanathan:
Novel Bi-partitioned Scan Architecture to Improve Transition Fault Coverage.
Asian Test Symposium 2005: 300-305 |
| 2 | EE | C. P. Ravikumar,
R. Dandamudi,
V. R. Devanathan,
N. Haldar,
K. Kiran,
P. S. Vijay Kumar:
A Framework for Distributed and Hierarchical Design-for-Test.
VLSI Design 2005: 497-503 |
| 2003 |
|---|
| 1 | EE | D. Janaki Ram,
M. A. Maluk Mohamed,
V. R. Devanathan:
A Framework for Concurrency Control in Real-Time Distributed Collaboration for Mobile Systems.
ICDCS Workshops 2003: 488-492 |
