| 2007 |
|---|
| 6 | EE | Matthias Beck,
Olivier Barondeau,
Martin Kaibel,
Frank Poehl,
Xijiang Lin,
Ron Press:
Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality
CoRR abs/0710.4763: (2007) |
| 2006 |
|---|
| 5 | EE | Ron Press,
Jay Jahangiri:
The Demand and Practical Approach for 100x Test Compression.
VLSI-SoC 2006: 245-250 |
| 2005 |
|---|
| 4 | EE | Jay Jahangiri,
Nilanjan Mukherjee,
Wu-Tung Cheng,
Subramanian Mahadevan,
Ron Press:
Achieving High Test Quality with Reduced Pin Count Testing.
Asian Test Symposium 2005: 312-317 |
| 3 | EE | Matthias Beck,
Olivier Barondeau,
Martin Kaibel,
Frank Poehl,
Xijiang Lin,
Ron Press:
Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality.
DATE 2005: 56-61 |
| 2 | EE | Matthias Beck,
Olivier Barondeau,
Frank Poehl,
Xijiang Lin,
Ron Press:
Measures to Improve Delay Fault Testing on Low-Cost Testers - A Case Study.
VTS 2005: 223-228 |
| 2003 |
|---|
| 1 | EE | Xijiang Lin,
Ron Press,
Janusz Rajski,
Paul Reuter,
Thomas Rinderknecht,
Bruce Swanson,
Nagesh Tamarapalli:
High-Frequency, At-Speed Scan Testing.
IEEE Design & Test of Computers 20(5): 17-25 (2003) |
