Tarang Vaish

List of publications from the DBLP Bibliography Server - FAQ

2005

1 EE Shantanu Gupta, Tarang Vaish, Santanu Chattopadhyay: Flip-flop chaining architecture for power-efficient scan during test application. Asian Test Symposium 2005: 410-413

2005
1	EE	Shantanu Gupta, Tarang Vaish, Santanu Chattopadhyay: Flip-flop chaining architecture for power-efficient scan during test application. Asian Test Symposium 2005: 410-413

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