2008 |
21 | EE | Masaru Fujita,
Haruhiko Takase,
Hidehiko Kita,
Terumine Hayashi:
Shape of error surfaces in SpikeProp.
IJCNN 2008: 840-844 |
2007 |
20 | | Kazutaka Noro,
Haruhiko Takase,
Hidehiko Kita,
Terumine Hayashi,
Naoki Morita:
Descriptive Answer Clustering System for Immediate Feedback.
ICCE 2007: 37-40 |
19 | EE | Haruhiko Takase,
Masahiko Masahiko,
Hidehiko Kita,
Terumine Hayashi:
Enhancing both generalization and fault tolerance of multilayer neural networks.
IJCNN 2007: 1429-1433 |
2005 |
18 | EE | Tsuyoshi Shinogi,
Hiroyuki Yamada,
Terumine Hayashi,
Shinji Tsuruoka,
Tomohiro Yoshikawa:
A Test Cost Reduction Method by Test Response and Test Vector Overlapping for Full-Scan Test Architecture.
Asian Test Symposium 2005: 366-371 |
17 | EE | Terumine Hayashi,
Haruna Yoshioka,
Tsuyoshi Shinogi,
Hidehiko Kita,
Haruhiko Takase:
On Test Data Compression Using Selective Don't-Care Identification.
J. Comput. Sci. Technol. 20(2): 210-215 (2005) |
2004 |
16 | EE | Terumine Hayashi,
Haruna Yoshioka,
Tsuyoshi Shinogi,
Hidehiko Kita,
Haruhiko Takase:
Test data compression technique using selective don't-care identification.
ASP-DAC 2004: 230-233 |
2003 |
15 | EE | Tsuyoshi Shinogi,
Yuki Yamada,
Terumine Hayashi,
Tomohiro Yoshikawa,
Shinji Tsuruoka:
Between-Core Vector Overlapping for Test Cost Reduction in Core Testing.
Asian Test Symposium 2003: 268-273 |
2001 |
14 | EE | Tsuyoshi Shinogi,
Tomokazu Kanbayashi,
Tomohiro Yoshikawa,
Shinji Tsuruoka,
Terumine Hayashi:
Faulty Resistance Sectioning Technique for Resistive Bridging Fault ATPG Systems.
Asian Test Symposium 2001: 76-81 |
13 | EE | Junzhi Sang,
Tsuyoshi Shinogi,
Haruhiko Takase,
Hidehiko Kita,
Terumine Hayashi:
An enhanced fault model for high defect coverage.
Systems and Computers in Japan 32(6): 36-44 (2001) |
2000 |
12 | EE | Tsuyoshi Shinogi,
Masahiro Ushio,
Terumine Hayashi:
Cyclic greedy generation method for limited number of IDDQ tests.
Asian Test Symposium 2000: 362- |
11 | EE | Haruhiko Takase,
Tsuyoshi Shinogi,
Terumine Hayashi,
Hidehiko Kita:
Evaluation Function for Fault Tolerant Multi-Layer Neural Networks.
IJCNN (3) 2000: 521-526 |
1999 |
10 | EE | Kai Zhang,
Tsuyoshi Shinogi,
Haruhiko Takase,
Terumine Hayashi:
A Method for Evaluating Upper Bound of Simultaneous Switching Gates Using Circuit Partition.
ASP-DAC 1999: 291-294 |
9 | EE | Tsuyoshi Shinogi,
Terumine Hayashi:
A Parallel Generation System of Compact IDDQ Test Sets for Large Combinational Circuits.
Asian Test Symposium 1999: 164- |
8 | EE | Tsuyoshi Shinogi,
Terumine Hayashi,
Kazuo Taki:
Test generation for stuck-on faults in pass-transistor logic SPL and implementation of DFT circuits.
Systems and Computers in Japan 30(7): 55-68 (1999) |
1998 |
7 | EE | Junzhi Sang,
Tsuyoshi Shinogi,
Haruhiko Takase,
Terumine Hayashi:
On a Logical Fault Model H1SGLF for Enhancing Defect Coverage.
Asian Test Symposium 1998: 102-107 |
6 | EE | Tsuyoshi Shinogi,
Terumine Hayashi:
A Simple and Efficient Method for Generating Compact IDDQ Test Set for Bridging Fault.
VTS 1998: 112-117 |
1997 |
5 | EE | Tsuyoshi Shinogi,
Terumine Hayashi,
Kazuo Taki:
Test Generation for Stuck-On Faults in BDD-Based Pass-Transistor Logic SPL.
Asian Test Symposium 1997: 16-21 |
1992 |
4 | | Kazumi Hatayama,
Kazunori Hikone,
Mitsuji Ikeda,
Terumine Hayashi:
Sequential Test Generation Based on Real-Value Logic.
ITC 1992: 41-48 |
1991 |
3 | | Yutaka Sekiyama,
Yasuyuki Fujihara,
Terumine Hayashi,
Mitsuho Seki,
Jiro Kusuhara,
Kazuhiko Iijima,
Masahiro Takakura,
Koji Fukatani:
Timing-Oriented Routers for PCB Layout Design of High-Performance Computers.
ICCAD 1991: 332-335 |
1989 |
2 | | Kazumi Hatayama,
Mitsuji Ikeda,
Terumine Hayashi,
Masahiro Takakura,
Kuniaki Kishida,
Shun Ishiyama:
Enhanced Delay Test Generator for High-Speed Logic LSIs.
ITC 1989: 161-165 |
1986 |
1 | EE | Kuniaki Kishida,
F. Shirotori,
Y. Ikemoto,
Shun Ishiyama,
Terumine Hayashi:
A delay test system for high speed logic LSI's.
DAC 1986: 786-790 |