Satoshi Ohtake

2008
24	EE	Masato Nakasato, Michiko Inoue, Satoshi Ohtake, Hideo Fujiwara: Design for Testability Method to Avoid Error Masking of Software-Based Self-Test for Processors. IEICE Transactions 91-D(3): 763-770 (2008)
2007
23	EE	Tsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko, Hideo Fujiwara: Efficient path delay test generation based on stuck-at test generation using checker circuitry. ICCAD 2007: 418-423
22	EE	Masato Nakasato, Satoshi Ohtake, Kewal K. Saluja, Hideo Fujiwara: Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability. IEICE Transactions 90-D(1): 296-305 (2007)
2006
21	EE	Mariane Comte, Satoshi Ohtake, Hideo Fujiwara, Michel Renovell: Electrical Behavior of GOS Fault affected Domino Logic Cell. DELTA 2006: 183-189
20	EE	Ilia Polian, Bernd Becker, Masato Nakasato, Satoshi Ohtake, Hideo Fujiwara: Low-Cost Hardening of Image Processing Applications Against Soft Errors. DFT 2006: 274-279
19	EE	Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara: A New Test Generation Model for Broadside Transition Testing of Partial Scan Circuits. VLSI-SoC 2006: 308-313
2005
18	EE	Yuki Yoshikaw, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara: Design for Testability Based on Single-Port-Change Delay Testing for Data Paths. Asian Test Symposium 2005: 254-259
17	EE	Hiroyuki Iwata, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara: A DFT Method for RTL Data Paths Based on Partially Strong Testability to Guarantee Complete Fault Efficiency. Asian Test Symposium 2005: 306-311
2004
16	EE	Debesh Kumar Das, Satoshi Ohtake, Hideo Fujiwara: New Non-Scan DFT Techniques to Achieve 100% Fault Efficiency. J. Electronic Testing 20(3): 315-323 (2004)
2003
15	EE	Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara: Reducibility of Sequential Test Generation to Combinational Test Generation for Several Delay Fault Models. Asian Test Symposium 2003: 58-63
14	EE	Satoshi Ohtake, Kouhei Ohtani, Hideo Fujiwara: A Method of Test Generation fo Path Delay Faults Using Stuck-at Fault Test Generation Algorithms. DATE 2003: 10310-10315
2002
13	EE	Atlaf Ul Amin, Satoshi Ohtake, Hideo Fujiwara: Design for Two-Pattern Testability of Controller-Data Path Circuits. Asian Test Symposium 2002: 73-79
12	EE	Satoshi Ohtake, Hideo Fujiwara, Shunjiro Miwa: A Method of Test Generation for Path Delay Faults in Balanced Sequential Circuits. VTS 2002: 321-327
11	EE	Satoshi Ohtake, Toshimitsu Masuzawa, Hideo Fujiwara: A nonscan DFT method for controllers to provide complete fault efficiency. Systems and Computers in Japan 33(5): 64-75 (2002)
2001
10	EE	Satoshi Ohtake, Shintaro Nagai, Hiroki Wada, Hideo Fujiwara: A DFT method for RTL circuits to achieve complete fault efficiency based on fixed-control testability. ASP-DAC 2001: 331-334
9	EE	Md. Altaf-Ul-Amin, Satoshi Ohtake, Hideo Fujiwara: Design for Hierarchical Two-Pattern Testability of Data Paths. Asian Test Symposium 2001: 11-16
8	EE	Debesh Kumar Das, Bhargab B. Bhattacharya, Satoshi Ohtake, Hideo Fujiwara: Testable Design of Sequential Circuits with Improved Fault Efficiency. VLSI Design 2001: 128-133
2000
7	EE	Satoshi Ohtake, Hiroki Wada, Toshimitsu Masuzawa, Hideo Fujiwara: A non-scan DFT method at register-transfer level to achieve complete fault efficiency. ASP-DAC 2000: 599-604
6	EE	Satoshi Ohtake, Toshimitsu Masuzawa, Hideo Fujiwara: A Non-Scan Approach to DFT for Controllers Achieving 100% Fault Efficiency. J. Electronic Testing 16(5): 553-566 (2000)
1999
5	EE	Debesh Kumar Das, Satoshi Ohtake, Hideo Fujiwara: New DFT Techniques of Non-Scan Sequential Circuits with Complete Fault Efficiency. Asian Test Symposium 1999: 263-268
4	EE	Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara: A Method of Test Generation for Weakly Testable Data Paths Using Test Knowledge Extracted from RTL Description. Asian Test Symposium 1999: 5-12
1998
3	EE	Satoshi Ohtake, Toshimitsu Masuzawa, Hideo Fujiwara: A Non-Scan DFT Method for Controllers to Achieve Complete Fault Efficiency. Asian Test Symposium 1998: 204-211
1997
2	EE	Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara: Sequential Test Generation Based on Circuit Pseudo-Transformation. Asian Test Symposium 1997: 62-67
1	EE	Hideo Fujiwara, Satoshi Ohtake, Tomoya Takasaki: A sequential circuit structure with combinational test generation complexity and its application. Systems and Computers in Japan 28(11): 11-21 (1997)

Coauthor Index

1	Md. Altaf-Ul-Amin	[9]
2	Atlaf Ul Amin	[13]
3	Bernd Becker	[20]
4	Bhargab B. Bhattacharya	[8]
5	Mariane Comte	[21]
6	Debesh Kumar Das (Debesh K. Das)	[5] [8] [16]
7	Hideo Fujiwara	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24]
8	Michiko Inoue	[4] [18] [24]
9	Tomoo Inoue	[2]
10	Tsuyoshi Iwagaki	[15] [19] [23]
11	Hiroyuki Iwata	[17]
12	Mineo Kaneko	[23]
13	Toshimitsu Masuzawa	[3] [6] [7] [11]
14	Shunjiro Miwa	[12]
15	Shintaro Nagai	[10]
16	Masato Nakasato	[20] [22] [24]
17	Kouhei Ohtani	[14]
18	Ilia Polian	[20]
19	Michel Renovell	[21]
20	Kewal K. Saluja	[22]
21	Tomoya Takasaki	[1]
22	Hiroki Wada	[7] [10]
23	Tomokazu Yoneda	[17]
24	Yuki Yoshikaw	[18]