Junichi Hirase

2005
12	EE	Junichi Hirase, Yoshiyuki Goi, Yoshiyuki Tanaka: IDDQ Testing Method using a Scan Pattern for Production Testing. Asian Test Symposium 2005: 18-21
11	EE	Junichi Hirase, Tatsuya Furukawa: Chip Identification using the Characteristic Dispersion of Transistor. Asian Test Symposium 2005: 188-193
2003
10	EE	Junichi Hirase: Test Pattern Length Required to Reach the Desired Fault Coverage. Asian Test Symposium 2003: 508
2002
9	EE	Junichi Hirase: High Precision Result Evaluation of VLSI. Asian Test Symposium 2002: 21-26
2001
8	EE	Junichi Hirase: Test Time Reduction through Minimum Execution of Tester-Hardware Setting Instructions. Asian Test Symposium 2001: 173-178
7	EE	Junichi Hirase: Yield Increase of VLSI after Redundancy-Repairing. Asian Test Symposium 2001: 353-358
2000
6	EE	Junichi Hirase, Shinichi Yoshimura: Faster processing for microprocessor functional ATPG. Asian Test Symposium 2000: 191-197
1999
5	EE	Junichi Hirase, Shinichi Yoshimura, Tomohisa Sczaki: Automatic Test Pattern Generation for Improving the Fault Coverage of Microprocessors. Asian Test Symposium 1999: 13-19
4	EE	Junichi Hirase, Naoki Shindou, Kouji Akahori: Scan Chain Diagnosis Using IDDQ Current Measurement. Asian Test Symposium 1999: 153-157
1998
3	EE	Junichi Hirase: Economical Importance of the Maximum Chip Area. Asian Test Symposium 1998: 64-
1995
2		Junichi Hirase: Improvement of the Defect Level of Micro-computer LSI Testing. ITC 1995: 377-383
1		Junichi Hirase: Study on the Costs of On-site VLSI Testing. ITC 1995: 438-443

Coauthor Index

1	Kouji Akahori	[4]
2	Tatsuya Furukawa	[11]
3	Yoshiyuki Goi	[12]
4	Tomohisa Sczaki	[5]
5	Naoki Shindou	[4]
6	Yoshiyuki Tanaka	[12]
7	Shinichi Yoshimura	[5] [6]

Colors in the list of coauthors