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Toshinori Hosokawa

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2005
15EEHideyuki Ichihara, Tomoo Inoue, Naoki Okamoto, Toshinori Hosokawa, Hideo Fujiwara: An Effective Design for Hierarchical Test Generation Based on Strong Testability. Asian Test Symposium 2005: 288-293
2003
14EEToshinori Hosokawa, Hiroshi Date, Masahide Miyazaki, Michiaki Muraoka, Hideo Fujiwara: A Method of Test Plan Grouping to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint. Asian Test Symposium 2003: 130-135
13EEMasahide Miyazaki, Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka, Hideo Fujiwara: A DFT Selection Method for Reducing Test Application Time of System-on-Chips. Asian Test Symposium 2003: 412-417
2002
12EEMasayoshi Yoshimura, Toshinori Hosokawa, Mitsuyasu Ohta: A Test Point Insertion Method to Reduce the Number of Test Patterns. Asian Test Symposium 2002: 298-304
11EEHiroshi Date, Toshinori Hosokawa, Michiaki Muraoka: A SoC Test Strategy Based on a Non-Scan DFT Method. Asian Test Symposium 2002: 305-310
10EEToshinori Hosokawa, Hiroshi Date, Michiaki Muraoka: A State Reduction Method for Non-Scan Based FSM Testing with Don't Care Inputs Identification Technique. Asian Test Symposium 2002: 55-60
9EEToshinori Hosokawa, Hiroshi Date, Michiaki Muraoka: A Test Generation Method Using a Compacted Test Table and a Test Generation Method Using a Compacted Test Plan Table for RTL Data Path Circuits. VTS 2002: 328-335
8EEToshinori Hosokawa, Tomoo Inoue, Toshihiro Hiraoka, Hideo Fujiwara: Test sequence compaction methods for acyclic sequential circuits using a time expansion model. Systems and Computers in Japan 33(10): 105-115 (2002)
2001
7EEToshinori Hosokawa, Masayoshi Yoshimura, Mitsuyasu Ohta: Design for testability strategies using full/partial scan designs and test point insertions to reduce test application times. ASP-DAC 2001: 485-491
1999
6EEToshinori Hosokawa, Toshihiro Hiraoka, Tomoo Inoue, Hideo Fujiwara: Static and Dynamic Test Sequence Compaction Methods for Acyclic Sequential Circuits Using a Time Expansion Model. Asian Test Symposium 1999: 192-
1998
5EETomoo Inoue, Toshinori Hosokawa, Takahiro Mihara, Hideo Fujiwara: An Optimal Time Expansion Model Based on Combinational ATPG for RT level Circuits. Asian Test Symposium 1998: 190-197
1997
4EEToshinori Hosokawa, Toshihiro Hiraoka, Mitsuyasu Ohta, Michiaki Muraoka, Shigeo Kuninobu: A Partial Scan Design Method Based on n-Fold Line-up Structures. Asian Test Symposium 1997: 306-
1996
3EEToshinori Hosokawa, Kenichi Kawaguchi, Mitsuyasu Ohta, Michiaki Muraoka: A Design for testability Method Using RTL Partitioning. Asian Test Symposium 1996: 88-93
1995
2EEAkira Motohara, Sadami Takeoka, Toshinori Hosokawa, Mitsuyasu Ohta, Yuji Takai, Michihiro Matsumoto, Michiaki Muraoka: Design for testability using register-transfer level partial scan selection. ASP-DAC 1995
1993
1EEAkira Motohara, Toshinori Hosokawa, Michiaki Muraoka, Hidetsugu Maekawa, Kazuhiro Kayashima, Yasuharu Shimeki, Seichi Shin: A State Traversal Algorithm Using a State Covariance Matrix. DAC 1993: 97-101

Coauthor Index

1Hiroshi Date [9] [10] [11] [13] [14]
2Hideo Fujiwara [5] [6] [8] [13] [14] [15]
3Toshihiro Hiraoka [4] [6] [8]
4Hideyuki Ichihara [15]
5Tomoo Inoue [5] [6] [8] [15]
6Kenichi Kawaguchi [3]
7Kazuhiro Kayashima [1]
8Shigeo Kuninobu [4]
9Hidetsugu Maekawa [1]
10Michihiro Matsumoto [2]
11Takahiro Mihara [5]
12Masahide Miyazaki [13] [14]
13Akira Motohara [1] [2]
14Michiaki Muraoka [1] [2] [3] [4] [9] [10] [11] [13] [14]
15Mitsuyasu Ohta [2] [3] [4] [7] [12]
16Naoki Okamoto [15]
17Yasuharu Shimeki [1]
18Seichi Shin [1]
19Yuji Takai [2]
20Sadami Takeoka [2]
21Masayoshi Yoshimura [7] [12]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)