| 2009 |
|---|
| 8 | EE | Keisuke Inoue,
Mineo Kaneko,
Tsuyoshi Iwagaki:
Safe clocking for the setup and hold timing constraints in datapath synthesis.
ACM Great Lakes Symposium on VLSI 2009: 27-32 |
| 2008 |
|---|
| 7 | EE | Keisuke Inoue,
Mineo Kaneko,
Tsuyoshi Iwagaki:
Safe clocking register assignment in datapath synthesis.
ICCD 2008: 120-127 |
| 6 | EE | Keisuke Inoue,
Mineo Kaneko,
Tsuyoshi Iwagaki:
Novel Register Sharing in Datapath for Structural Robustness against Delay Variation.
IEICE Transactions 91-A(4): 1044-1053 (2008) |
| 2007 |
|---|
| 5 | EE | Tsuyoshi Iwagaki,
Satoshi Ohtake,
Mineo Kaneko,
Hideo Fujiwara:
Efficient path delay test generation based on stuck-at test generation using checker circuitry.
ICCAD 2007: 418-423 |
| 2006 |
|---|
| 4 | EE | Tsuyoshi Iwagaki,
Satoshi Ohtake,
Hideo Fujiwara:
A New Test Generation Model for Broadside Transition Testing of Partial Scan Circuits.
VLSI-SoC 2006: 308-313 |
| 3 | EE | Zhiqiang You,
Tsuyoshi Iwagaki,
Michiko Inoue,
Hideo Fujiwara:
A Low Power Deterministic Test Using Scan Chain Disable Technique.
IEICE Transactions 89-D(6): 1931-1939 (2006) |
| 2005 |
|---|
| 2 | EE | Kazuko Kambe,
Michiko Inoue,
Hideo Fujiwara,
Tsuyoshi Iwagaki:
Efficient Constraint Extraction for Template-Based Processor Self-Test Generation.
Asian Test Symposium 2005: 444-449 |
| 2003 |
|---|
| 1 | EE | Tsuyoshi Iwagaki,
Satoshi Ohtake,
Hideo Fujiwara:
Reducibility of Sequential Test Generation to Combinational Test Generation for Several Delay Fault Models.
Asian Test Symposium 2003: 58-63 |
