| 2008 |
|---|
| 5 | EE | Bei Cao,
Liyi Xiao,
Yong-sheng Wang:
A Low Power Deterministic Test Pattern Generator for BIST Based on Cellular Automata.
DELTA 2008: 266-269 |
| 4 | EE | Jing-hu Li,
Yu-nan Fu,
Yong-sheng Wang:
A 1-V piecewise curvature-corrected CMOS bandgap reference.
ISLPED 2008: 289-294 |
| 2007 |
|---|
| 3 | EE | Bin Zhou,
Yizheng Ye,
Yong-sheng Wang:
Simultaneous reduction in test data volume and test time for TRC-reseeding.
ACM Great Lakes Symposium on VLSI 2007: 49-54 |
| 2005 |
|---|
| 2 | EE | Yong-sheng Wang,
Jinxiang Wang,
Feng-chang Lai,
Yizheng Ye:
Optimal Schemes for ADC BIST Based on Histogram.
Asian Test Symposium 2005: 52-57 |
| 2003 |
|---|
| 1 | EE | Yong-sheng Wang,
Liyi Xiao,
Mingyan Yu,
Jinxiang Wang,
Yizheng Ye:
A Test Architecture for System-on-a-Chip.
Asian Test Symposium 2003: 506 |
