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Yong-sheng Wang

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2008
5EEBei Cao, Liyi Xiao, Yong-sheng Wang: A Low Power Deterministic Test Pattern Generator for BIST Based on Cellular Automata. DELTA 2008: 266-269
4EEJing-hu Li, Yu-nan Fu, Yong-sheng Wang: A 1-V piecewise curvature-corrected CMOS bandgap reference. ISLPED 2008: 289-294
2007
3EEBin Zhou, Yizheng Ye, Yong-sheng Wang: Simultaneous reduction in test data volume and test time for TRC-reseeding. ACM Great Lakes Symposium on VLSI 2007: 49-54
2005
2EEYong-sheng Wang, Jinxiang Wang, Feng-chang Lai, Yizheng Ye: Optimal Schemes for ADC BIST Based on Histogram. Asian Test Symposium 2005: 52-57
2003
1EEYong-sheng Wang, Liyi Xiao, Mingyan Yu, Jinxiang Wang, Yizheng Ye: A Test Architecture for System-on-a-Chip. Asian Test Symposium 2003: 506

Coauthor Index

1Bei Cao [5]
2Yu-nan Fu [4]
3Feng-chang Lai [2]
4Jing-hu Li [4]
5Jinxiang Wang [1] [2]
6Liyi Xiao [1] [5]
7Yizheng Ye [1] [2] [3]
8Mingyan Yu [1]
9Bin Zhou [3]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)