Kailasnath Maneparambil

2007
2	EE	Sasidhar Sunkari, Supratik Chakraborty, Vivekananda M. Vedula, Kailasnath Maneparambil: A Scalable Symbolic Simulator for Verilog RTL. MTV 2007: 51-59
2005
1	EE	K. Uday Bhaskar, M. Prasanth, V. Kamakoti, Kailasnath Maneparambil: A Framework for Automatic Assembly Program Generator (A2PG) for Verification and Testing of Processor Cores. Asian Test Symposium 2005: 40-45

Coauthor Index

1	K. Uday Bhaskar	[1]
2	Supratik Chakraborty	[2]
3	V. Kamakoti	[1]
4	M. Prasanth	[1]
5	Sasidhar Sunkari	[2]
6	Vivekananda M. Vedula	[2]