| 2008 |
|---|
| 6 | EE | Ajoy Kumar Palit,
Kishore K. Duganapalli,
Walter Anheier:
Crosstalk fault modeling in defective pair of interconnects.
Integration 41(1): 27-37 (2008) |
| 2007 |
|---|
| 5 | | Ajoy Kumar Palit,
Kishore K. Duganapalli,
Walter Anheier:
XSIM: An Efficient Crosstalk Simulator for Analysis and Modeling of Signal Integrity Faults in Both Defective and Defect-free Interconnects.
DDECS 2007: 161-164 |
| 4 | EE | Shyam Praveen Vudathu,
Kishore K. Duganapalli,
Rainer Laur,
D. Kubalinska,
Angelika Bunse-Gerstner:
Parametric Yield Analysis of Mems via Statistical Methods
CoRR abs/0711.3287: (2007) |
| 2006 |
|---|
| 3 | EE | Ajoy Kumar Palit,
Kishore K. Duganapalli,
Walter Anheier:
Influence of Resistive Bridging Fault on Crosstalk Coupling Effects in On-Chip Aggressor-Victim Interconnects.
DFT 2006: 336-344 |
| 2 | EE | Ajoy Kumar Palit,
Kishore K. Duganapalli,
Walter Anheier:
Modeling of Crosstalk Fault in Defective Interconnects.
PATMOS 2006: 340-349 |
| 2005 |
|---|
| 1 | EE | Ajoy Kumar Palit,
Lei Wu,
Kishore K. Duganapalli,
Walter Anheier,
Jürgen Schlöffel:
A New, Flexible and Very Accurate Crosstalk Fault Model to Analyze the Effects of Coupling Noise between the Interconnects on Signal Integrity Losses in Deep Submicron Chips.
Asian Test Symposium 2005: 22-27 |
