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Hadi Esmaeilzadeh

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2006
9EEHadi Esmaeilzadeh, A. Moghimi, E. Ebrahimi, Caro Lucas, Zainalabedin Navabi, A. M. Fakhraie: DCim++: a C++ library for object oriented hardware design and distributed simulation. ISCAS 2006
8EEHadi Esmaeilzadeh, Pooya Saeedi, Babak Nadjar Araabi, Caro Lucas, Seid Mehdi Fakhraie: Neural network stream processing core (NnSP) for embedded systems. ISCAS 2006
7EESaeed Safari, Amir-Hossein Jahangir, Hadi Esmaeilzadeh: A parameterized graph-based framework for high-level test synthesis. Integration 39(4): 363-381 (2006)
2005
6EEHadi Esmaeilzadeh, Saeed Shamshiri, Pooya Saeedi, Zainalabedin Navabi: ISC: Reconfigurable Scan-Cell Architecture for Low Power Testing. Asian Test Symposium 2005: 236-241
5EESaeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi: Instruction-level test methodology for CPU core self-testing. ACM Trans. Design Autom. Electr. Syst. 10(4): 673-689 (2005)
2004
4EESaeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi: Test Instruction Set (TIS) for High Level Self-Testing of CPU Cores. Asian Test Symposium 2004: 158-163
3 Neda Shahidi, Hadi Esmaeilzadeh, Marziye Abdollahi, Caro Lucas: Memetic Algorithm Based Path Planning for a Mobile Robot. International Conference on Computational Intelligence 2004: 56-59
2003
2EESaeed Safari, Hadi Esmaeilzadeh, Amir-Hossein Jahangir: Testability Improvement During High-Level Synthesis. Asian Test Symposium 2003: 505
1EESaeed Safari, Hadi Esmaeilzadeh, Amir-Hossein Jahangir: A novel improvement technique for high-level test synthesis. ISCAS (5) 2003: 609-612

Coauthor Index

1Marziye Abdollahi [3]
2Babak Nadjar Araabi [8]
3E. Ebrahimi [9]
4A. M. Fakhraie [9]
5Seid Mehdi Fakhraie [8]
6Amir-Hossein Jahangir [1] [2] [7]
7Caro Lucas [3] [8] [9]
8A. Moghimi [9]
9Zainalabedin Navabi [4] [5] [6] [9]
10Pooya Saeedi [6] [8]
11Saeed Safari [1] [2] [7]
12Neda Shahidi [3]
13Saeed Shamshiri [4] [5] [6]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)