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Victor Kim

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2004
6 Prithviraj Banerjee, Malay Haldar, Anshuman Nayak, Victor Kim, Vikram Saxena, Steven Parkes, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi, David Zaretsky, R. Anderson, J. R. Uribe: Overview of a compiler for synthesizing MATLAB programs onto FPGAs. IEEE Trans. VLSI Syst. 12(3): 312-324 (2004)
2003
5EEPrithviraj Banerjee, Debabrata Bagchi, Malay Haldar, Anshuman Nayak, Victor Kim, R. Uribe: Automatic Conversion of Floating Point MATLAB Programs into Fixed Point FPGA Based Hardware Design. FCCM 2003: 263-264
4EEPrithviraj Banerjee, Vikram Saxena, J. R. Uribe, Malay Haldar, Anshuman Nayak, Victor Kim, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi, R. Anderson: Making area-performance tradeoffs at the high level using the AccelFPGA compiler for FPGAs. FPGA 2003: 237
2002
3EEPrithviraj Banerjee, Malay Haldar, Anshuman Nayak, Victor Kim, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi: A Behavioral Synthesis Tool for Exploiting Fine Grain Parallelism in FPGAs. IWDC 2002: 246-256
2000
2EEVictor Kim, Prithviraj Banerjee, Kaushik De: Fine-Grained Parallel VLSI Synthesis for Commercial CAD on a Network of Workstations. ICPP 2000: 421-
1998
1EEVictor Kim, Prithviraj Banerjee: Parallel Algorithms for Power Estimation. DAC 1998: 672-677

Coauthor Index

1R. Anderson [4] [6]
2Debabrata Bagchi [3] [4] [5] [6]
3Prithviraj Banerjee (Prith Banerjee) [1] [2] [3] [4] [5] [6]
4Kaushik De [2]
5Malay Haldar [3] [4] [5] [6]
6Anshuman Nayak [3] [4] [5] [6]
7Satrajit Pal [3] [4] [6]
8Steven Parkes [6]
9Vikram Saxena [4] [6]
10Nikhil Tripathi [3] [4] [6]
11J. R. Uribe [4] [6]
12R. Uribe [5]
13David Zaretsky [6]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)