| 2008 |
|---|
| 21 | EE | Wei-Chen Huang,
Chen-Ming Hsu,
Chien-Ming Lee,
Hong-Yi Huang,
Ching-Hsing Luo:
Dual band LNA/mixer using conjugate matching for implantable biotelemetry.
ISCAS 2008: 1764-1767 |
| 20 | EE | Hong-Yi Huang,
Chia-Ming Liang,
Shi-Jia Sun:
Low-power 50% duty cycle corrector.
ISCAS 2008: 2362-2365 |
| 19 | EE | Hong-Yi Huang,
Li-Wei Huang,
Wei-Sheng Tseng,
Chih-Yuan Hsu:
A 6-Gbit/s SATA spread-spectrum clock generator using two-stage delta-sigma modulator.
SoCC 2008: 333-336 |
| 18 | EE | Hong-Yi Huang,
Yi-Jui Tsai,
Kung-Liang Ho,
Chan-Yu Lin:
All digital time-to-digital converter using single delay-locked loop.
SoCC 2008: 341-344 |
| 2007 |
|---|
| 17 | EE | Hong-Yi Huang,
Sheng-Da Wu,
Yi-Jui Tsai:
A New Cycle-Time-to-Digital Converter With Two Level Conversion Scheme.
ISCAS 2007: 2160-2163 |
| 2006 |
|---|
| 16 | EE | Hong-Yi Huang,
Chia-Ming Liang,
Wei-Ming Chiu:
1-99% input duty 50% output duty cycle corrector.
ISCAS 2006 |
| 15 | EE | Hong-Yi Huang,
Bo-Ruei Wang,
Jen-Chieh Liu:
High-gain and high-bandwidth rail-to-rail operational amplifier with slew rate boost circuit.
ISCAS 2006 |
| 14 | EE | Hong-Yi Huang,
Ching-Chieh Wu,
Sen-Da Wu:
On-chip bidirectional transceiver.
ISCAS 2006 |
| 2005 |
|---|
| 13 | EE | Hong-Yi Huang,
Sheng-Fen Ho,
Li-Wei Huang:
A 64-MHz/spl sim/1920-MHz programmable spread-spectrum clock generator.
ISCAS (4) 2005: 3363-3366 |
| 2004 |
|---|
| 12 | EE | Chun-Jen Huang,
Hong-Yi Huang:
A low-voltage CMOS rail-to-rail operational amplifier using double p-channel differential input pairs.
ISCAS (1) 2004: 673-676 |
| 11 | EE | Hong-Yi Huang,
Shih-Lun Chen:
Interconnect accelerating techniques for sub-100-nm gigascale systems.
IEEE Trans. VLSI Syst. 12(11): 1192-1200 (2004) |
| 2003 |
|---|
| 10 | EE | Chin-Shan Hsieh,
Hong-Yi Huang,
Jeng-Dang Juan,
Ruey-Nan Yeh:
A high-bandwidth wireless infrared receiver with feedforward offset extractor.
ISCAS (1) 2003: 73-76 |
| 2002 |
|---|
| 9 | EE | Hong-Yi Huang,
Jing-Fu Lin:
Multiple bulk input differential logic.
APCCAS (1) 2002: 461-464 |
| 8 | EE | Hong-Yi Huang,
Shih-Lun Chen:
Threshold triggers and accelerator for deep submicron interconnection.
APCCAS (2) 2002: 143-146 |
| 7 | EE | Hong-Yi Huang,
Jing-Fu Lin:
CMOS bulk input technique.
ISCAS (3) 2002: 253-256 |
| 6 | EE | Hong-Yi Huang,
Shih-Lun Chen:
Input isolated sense amplifiers.
ISCAS (4) 2002: 587-590 |
| 5 | EE | Hong-Yi Huang,
Hsuan-Yi Su:
Low-power 2P2N SRAM with column hidden refresh.
ISCAS (4) 2002: 591-594 |
| 2001 |
|---|
| 4 | EE | Hong-Yi Huang,
Teng-Neng Wang:
High-speed CMOS logic circuits in capacitor coupling technique.
ISCAS (4) 2001: 634-637 |
| 1995 |
|---|
| 3 | | Hong-Yi Huang,
Jinn-Shyan Wang,
Yuan-Hua Chu,
Tain-Shun Wu,
Kuo-Hsing Cheng,
Chung-Yu Wu:
Low-Voltage Low-Power CMOS True-Single-Phase Clocking Scheme with Locally Asynchronous Logic Circuits.
ISCAS 1995: 1572-1575 |
| 1994 |
|---|
| 2 | | Hong-Yi Huang,
Chung-Yu Wu:
New CMOS Differential Logic Circuits for True-Single-Phase Pipelined Systems.
ISCAS 1994: 15-18 |
| 1993 |
|---|
| 1 | | Hong-Yi Huang,
Chung-Yu Wu:
Redundant Algebra and Integrated Circuit Implementation of Ternary Logic and Their Applications.
ISCAS 1993: 1905-1908 |
