| 2008 |
|---|
| 36 | EE | Kazuhiro Nakamura,
Masatoshi Yamamoto,
Kazuyoshi Takagi,
Naofumi Takagi:
Fast and memory efficient VLSI architecture for output probability computations of HMM-based recognition systems.
ISCAS 2008: 1688-1691 |
| 35 | EE | Marcelo E. Kaihara,
Naofumi Takagi:
Bipartite Modular Multiplication Method.
IEEE Trans. Computers 57(2): 157-164 (2008) |
| 34 | EE | Naofumi Takagi,
Kazuaki Murakami,
Akira Fujimaki,
Nobuyuki Yoshikawa,
Koji Inoue,
Hiroaki Honda:
Proposal of a Desk-Side Supercomputer with Reconfigurable Data-Paths Using Rapid Single-Flux-Quantum Circuits.
IEICE Transactions 91-C(3): 350-355 (2008) |
| 2007 |
|---|
| 33 | EE | Katsuki Kobayashi,
Naofumi Takagi,
Kazuyoshi Takagi:
An Algorithm for Inversion in GF(2^m) Suitable for Implementation Using a Polynomial Multiply Instruction on GF(2).
IEEE Symposium on Computer Arithmetic 2007: 105-112 |
| 32 | EE | Koji Obata,
Kazuyoshi Takagi,
Naofumi Takagi:
Logic Synthesis Method for Dual-Rail RSFQ Digital Circuits Using Root-Shared Binary Decision Diagrams.
IEICE Transactions 90-A(1): 257-266 (2007) |
| 31 | EE | Koji Obata,
Kazuyoshi Takagi,
Naofumi Takagi:
A Method of Sequential Circuit Synthesis Using One-Hot Encoding for Single-Flux-Quantum Digital Circuits.
IEICE Transactions 90-C(12): 2278-2284 (2007) |
| 2006 |
|---|
| 30 | EE | Naofumi Takagi,
Shunsuke Kadowaki,
Kazuyoshi Takagi:
A Hardware Algorithm for Integer Division Using the SD2 Representation.
IEICE Transactions 89-A(10): 2874-2881 (2006) |
| 29 | EE | Fumio Kumazawa,
Naofumi Takagi:
Hardware Algorithm for Computing Reciprocal of Euclidean Norm of a 3-D Vector.
IEICE Transactions 89-A(6): 1799-1806 (2006) |
| 2005 |
|---|
| 28 | EE | Marcelo E. Kaihara,
Naofumi Takagi:
Bipartite Modular Multiplication.
CHES 2005: 201-210 |
| 27 | EE | Naofumi Takagi,
Shunsuke Kadowaki,
Kazuyoshi Takagi:
A Hardware Algorithm for Integer Division.
IEEE Symposium on Computer Arithmetic 2005: 140-146 |
| 26 | EE | Marcelo E. Kaihara,
Naofumi Takagi:
A Hardware Algorithm for Modular Multiplication/Division.
IEEE Trans. Computers 54(1): 12-21 (2005) |
| 25 | EE | Marcelo E. Kaihara,
Naofumi Takagi:
A Hardware Algorithm for Modular Multiplication/Division Based on the Extended Euclidean Algorithm.
IEICE Transactions 88-A(12): 3610-3617 (2005) |
| 2004 |
|---|
| 24 | | Nhon T. Quach,
Naofumi Takagi,
Michael J. Flynn:
Systematic IEEE rounding method for high-speed floating-point multipliers.
IEEE Trans. VLSI Syst. 12(5): 511-521 (2004) |
| 2003 |
|---|
| 23 | EE | Marcelo E. Kaihara,
Naofumi Takagi:
A VLSI Algorithm for Modular Multiplication/Division.
IEEE Symposium on Computer Arithmetic 2003: 220-227 |
| 2002 |
|---|
| 22 | EE | Naofumi Takagi:
Multiple-Valued-Digit Number Representations in Arithmetic Circuit Algorithms.
ISMVL 2002: 224- |
| 21 | EE | Hiroto Yasuura,
Naofumi Takagi,
Srivaths Ravi,
Michael Torla,
Catherine H. Gebotys:
Special Session: Security on SoC.
ISSS 2002: 192-194 |
| 2001 |
|---|
| 20 | EE | Naofumi Takagi:
A Hardware Algorithm for Computing Reciprocal Square Root.
IEEE Symposium on Computer Arithmetic 2001: 94-100 |
| 19 | EE | Naofumi Takagi,
Jun-ichi Yoshiki,
Kazuyoshi Takagi:
A Fast Algorithm for Multiplicative Inversion in GF(2m) Using Normal Basis.
IEEE Trans. Computers 50(5): 394-398 (2001) |
| 2000 |
|---|
| 18 | EE | Naofumi Takagi,
Seiji Kuwahara:
A VLSI Algorithm for Computing the Euclidean Norm of a 3D Vector.
IEEE Trans. Computers 49(10): 1074-1082 (2000) |
| 17 | EE | Akira Higuchi,
Naofumi Takagi:
A fast addition algorithm for elliptic curve arithmetic in GF(2n) using projective coordinates.
Inf. Process. Lett. 76(3): 101-103 (2000) |
| 1999 |
|---|
| 16 | EE | Naofumi Takagi,
Seiji Kuwahara:
Digit-Recurrence Algorithm for Computing Euclidean Norm of a 3-D Vector.
IEEE Symposium on Computer Arithmetic 1999: 86- |
| 15 | EE | Naofumi Takagi,
Takashi Horiyama:
A High-Speed Reduced-Size Adder Under Left-to-Right Input Arrival.
IEEE Trans. Computers 48(1): 76-80 (1999) |
| 1998 |
|---|
| 14 | | Naofumi Takagi:
Powering by a Table Look-Up and a Multiplication with Operand Modification.
IEEE Trans. Computers 47(11): 1216-1222 (1998) |
| 1997 |
|---|
| 13 | EE | Naofumi Takagi:
Generating a Power of an Operand by a Table Look-up and a Multiplication.
IEEE Symposium on Computer Arithmetic 1997: 126-131 |
| 12 | | Massayuki Ito,
Naofumi Takagi,
Shuzo Yajima:
Efficient Initial Approximation for Multiplicative Division and Square Root by a Multiplication with Operand Modification.
IEEE Trans. Computers 46(4): 495-498 (1997) |
| 11 | | Takafumi Hamano,
Naofumi Takagi,
Shuzo Yajima,
Franco P. Preparata:
O(n)-Depth Modular Exponentiation Circuit Algorithm.
IEEE Trans. Computers 46(6): 701-704 (1997) |
| 1996 |
|---|
| 10 | EE | Masayuki Ito,
Naofumi Takagi,
Shuzo Yajima:
Square Rooting by Iterative Multiply-Additions.
Inf. Process. Lett. 60(5): 267-269 (1996) |
| 1995 |
|---|
| 9 | EE | Hannes Hassler,
Naofumi Takagi:
Function Evaluation by Table Look-up and Addition.
IEEE Symposium on Computer Arithmetic 1995: 10-16 |
| 8 | EE | Takafumi Hamano,
Naofumi Takagi,
Shuzo Yajima,
Franco P. Preparata:
O(n)-depth circuit algorithm for modular exponentiation.
IEEE Symposium on Computer Arithmetic 1995: 188-192 |
| 7 | EE | Masayuki Ito,
Naofumi Takagi,
Shuzo Yajima:
Efficient Initial Approximation and Fast Converging Methods for Division and Square Root.
IEEE Symposium on Computer Arithmetic 1995: 2-8 |
| 1992 |
|---|
| 6 | | Naofumi Takagi,
Shuzo Yajima:
Modular Multiplication Hardware Algorithms with a Redundant Representation and Their Application to RSA Cryptosystem.
IEEE Trans. Computers 41(7): 887-891 (1992) |
| 5 | | Naofumi Takagi:
A Radix-4 Modular Multiplication Hardware Algorithm for Modular Exponentiation.
IEEE Trans. Computers 41(8): 949-956 (1992) |
| 1991 |
|---|
| 4 | | Naofumi Takagi,
Tohru Asada,
Shuzo Yajima:
Redundant CORDIC Methods with a Constant Scale Factor for Sine and Cosine Computation.
IEEE Trans. Computers 40(9): 989-995 (1991) |
| 1987 |
|---|
| 3 | | Naofumi Takagi,
Shuzo Yajima:
On-Line Error-Detectable High-Speed Multiplier Using Redundant Binary Representation and Three-Rail Logic.
IEEE Trans. Computers 36(11): 1310-1317 (1987) |
| 1985 |
|---|
| 2 | | Naofumi Takagi,
Hiroto Yasuura,
Shuzo Yajima:
High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree.
IEEE Trans. Computers 34(9): 789-796 (1985) |
| 1982 |
|---|
| 1 | | Hiroto Yasuura,
Naofumi Takagi,
Shuzo Yajima:
The Parallel Enumeration Sorting Scheme for VLSI.
IEEE Trans. Computers 31(12): 1192-1201 (1982) |
