A. Valentian
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2004
1
EE
A. Valentian,
O. Thomas
,
Andrei Vladimirescu
,
Amara Amara
: Modeling subthreshold SOI logic for static timing analysis.
IEEE Trans. VLSI Syst. 12
(6): 662-669 (2004)
Coauthor
Index
1
Amara Amara
[
1
]
2
O. Thomas
[
1
]
3
Andrei Vladimirescu
[
1
]
Copyright ©
Sun May 17 03:24:02 2009 by
Michael Ley
(
ley@uni-trier.de
)