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A. Valentian

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2004
1EEA. Valentian, O. Thomas, Andrei Vladimirescu, Amara Amara: Modeling subthreshold SOI logic for static timing analysis. IEEE Trans. VLSI Syst. 12(6): 662-669 (2004)

Coauthor Index

1Amara Amara [1]
2O. Thomas [1]
3Andrei Vladimirescu [1]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)