| 2004 |
|---|
| 10 | EE | Noriaki Suzuki,
Shunsuke Kurotaki,
Masayasu Suzuki,
Naoto Kaneko,
Yutaka Yamada,
Katsuaki Deguchi,
Yohei Hasegawa,
Hideharu Amano,
Kenichiro Anjo,
Masato Motomura,
Kazutoshi Wakabayashi,
Takeo Toi,
Toru Awashima:
Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor.
FCCM 2004: 328-329 |
| 9 | EE | Mahmoud Meribout,
Masato Motomura:
A Combined Approach to High-Level Synthesis for Dynamically Reconfigurable Systems.
IEEE Trans. Computers 53(12): 1508-1522 (2004) |
| 8 | EE | Mahmoud Meribout,
Masato Motomura:
Efficient metrics and high-level synthesis for dynamically reconfigurable logic.
IEEE Trans. VLSI Syst. 12(6): 603-621 (2004) |
| 2003 |
|---|
| 7 | EE | Mahmoud Meribout,
Masato Motomura:
A New Reconfigurable Hardware Architecture for High Throughput Networking Applications and its Design Methodology.
IPDPS 2003: 182 |
| 6 | | Mahmoud Meribout,
Masato Motomura:
A New Hardware Algorithm for Fast IP Routing Targeting Programmable Routers.
Net-Con 2003: 164-179 |
| 5 | EE | Mahmoud Meribout,
Masato Motomura:
New design methodology with efficient prediction of quality metrics for logic level design towards dynamic reconfigurable logic.
Journal of Systems Architecture 48(8-10): 285-310 (2003) |
| 2000 |
|---|
| 4 | EE | Masakazu Yamashina,
Masato Motomura:
Reconfigurable computing: its concept and a practical embodiment using newly developed dynamically reconfigurable logic (DRL) LSI: invited talk.
ASP-DAC 2000: 329-332 |
| 3 | EE | Yuichiro Shibata,
Masaki Uno,
Hideharu Amano,
K. Furuta,
Taro Fujii,
Masato Motomura:
A Virtual Hardware System on a Dynamically Reconfigurable Logic Device.
FCCM 2000: 295-296 |
| 2 | EE | Lars Friebe,
Yoshikazu Yabe,
Masato Motomura:
A Study of Channeled DRAM Memory Architectures.
ICCD 2000: 261-266 |
| 1998 |
|---|
| 1 | EE | Masato Motomura,
Yoshiharu Aimoto,
Atsufkni Shibayama,
Yoshikazu Yabe,
Masakazu Yamashina:
An Embedded DRAM-FPGA Chip with Instantaneous Logic Reconfiguration.
FCCM 1998: 264-266 |
