| 2008 |
|---|
| 11 | EE | Bastien Giraud,
Amara Amara:
Read Stability and Write Ability Tradeoff for 6T SRAM Cells in Double-Gate CMOS.
DELTA 2008: 201-204 |
| 10 | EE | Bastien Giraud,
Amara Amara:
A novel 4T asymmetric single-ended SRAM cell in sub-32 nm double gate technology.
ISCAS 2008: 1906-1909 |
| 2007 |
|---|
| 9 | EE | Bastien Giraud,
Amara Amara,
Andrei Vladimirescu:
A Comparative Study of 6T and 4T SRAM Cells in Double-Gate CMOS with Statistical Variation.
ISCAS 2007: 3022-3025 |
| 2006 |
|---|
| 8 | EE | Amara Amara,
Frederic Amiel,
Thomas Ea:
FPGA vs. ASIC for low power applications.
Microelectronics Journal 37(8): 669-677 (2006) |
| 2005 |
|---|
| 7 | EE | Florence Rossant,
Frederic Amiel,
Thomas Ea,
Amara Amara,
Manuel Torres Eslava:
Iris identification and robustness evaluation of a wavelet packets based algorithm.
ICIP (3) 2005: 257-260 |
| 6 | EE | O. Thomas,
Amara Amara:
Ultra low voltage design considerations of SOI SRAM memory cells.
ISCAS (4) 2005: 4094-4097 |
| 2004 |
|---|
| 5 | EE | Erik Rydgren,
Thomas Ea,
Frederic Amiel,
Florence Rossant,
Amara Amara:
IRIS features extraction using wavelet packets.
ICIP 2004: 861-864 |
| 4 | EE | A. Valentian,
O. Thomas,
Andrei Vladimirescu,
Amara Amara:
Modeling subthreshold SOI logic for static timing analysis.
IEEE Trans. VLSI Syst. 12(6): 662-669 (2004) |
| 2003 |
|---|
| 3 | EE | Olivier Thomas,
Amara Amara:
An SOI 4 transistors self-refresh ultra-low-voltage memory cell.
ISCAS (5) 2003: 401-404 |
| 2001 |
|---|
| 2 | EE | A. Turier,
L. Ben Ammar,
Amara Amara:
Static power consumption management in CMOS memories.
ISCAS (4) 2001: 506-509 |
| 1996 |
|---|
| 1 | EE | Philippe Royannez,
Amara Amara:
A 1.0ns 64-bits GaAs Adder using Quad tree algorithm.
Great Lakes Symposium on VLSI 1996: 24-28 |
