| 2008 |
|---|
| 4 | EE | Yen-Liang Chen,
Ming-Feng Hsu,
Jyh-Ting Lai,
An-Yeu Wu:
Cost-Effective Joint Echo-NEXT Canceller Designs for 10GBase-T Ethernet Systems Based on a Shortened Impulse Response Filter (SIRF) Scheme.
Signal Processing Systems 52(1): 59-73 (2008) |
| 2007 |
|---|
| 3 | EE | Jyh-Ting Lai,
An-Yeu Wu,
Chien-Hsiung Lee:
Joint AGC-Equalization Algorithm and VLSI Architecture for Wirelined Transceiver Designs.
IEEE Trans. VLSI Syst. 15(2): 236-240 (2007) |
| 2004 |
|---|
| 2 | | Hsiu-Ping Lin,
Nancy Fang-Yih Chen,
Jyh-Ting Lai,
An-Yeu Wu:
1000BASE-T Gigabit Ethernet baseband DSP IC design.
ISCAS (4) 2004: 401-404 |
| 1 | | Meng-Da Yang,
An-Yeu Wu,
Jyh-Ting Lai:
High-performance VLSI architecture of adaptive decision feedback equalizer based on predictive parallel branch slicer (PPBS) scheme.
IEEE Trans. VLSI Syst. 12(2): 218-226 (2004) |
