Roberto Saletti

2007
14	EE	D. Audino, F. Baronti, A. Lazzeri, Roberto Roncella, Roberto Saletti: FPGA/DSP-based Configurable Multi-Channel Counter. DSD 2007: 376-382
13	EE	F. Baronti, F. Lenzi, Roberto Roncella, Roberto Saletti: A Hardware-Software Platform for Design and Verification of In-Motorcycle Electronic Systems. DSD 2007: 440-443
12	EE	F. Baronti, Roberto Roncella, Roberto Saletti, P. D'Abramo, L. Di Piro, H. Fabian, M. Giardi: The importance of At-Speed Scan Testing: an industrial experience. DSD 2007: 672-675
2006
11	EE	F. Baronti, P. D'Abramo, M. Knaipp, R. Minixhofer, Roberto Roncella, Roberto Saletti, M. Schrems, R. Serventi, V. Vescoli: FlexRay transceiver in a 0.35 µm CMOS high-voltage technology. DATE Designers' Forum 2006: 201-205
2004
10	EE	Andrea S. Brogna, Franco Bigongiari, Fabrizio Bertuccelli, Walter Errico, Simone Giovannetti, Egidio Pescari, Roberto Saletti: SEU Protected CPU for Slow Control on Space Vehicles. DELTA 2004: 422-424
9	EE	Antonio Blotti, Roberto Saletti: Ultralow-power adiabatic circuit semi-custom design. IEEE Trans. VLSI Syst. 12(11): 1248-1253 (2004)
2003
8	EE	Fabrizio Bertuccelli, Franco Bigongiari, Andrea S. Brogna, Giorgio Di Natale, Paolo Prinetto, Roberto Saletti: Exhaustive Test of Several Dependable Memory Architectures Designed by GRAAL Tool. Asian Test Symposium 2003: 32-37
7		G. Bonfini, C. Garbossa, Roberto Saletti: A Switched Opamp-based 10-b Integrated ADC for Ultra Low-power Applications. VLSI-SOC 2003: 136-141
6		Andrea S. Brogna, Franco Bigongiari, Silvia Chiusano, Paolo Prinetto, Roberto Saletti: Designing and Testing High Dependable Memories for Aerospace Applications. VLSI-SOC 2003: 221-
2002
5	EE	Antonio Blotti, Maurizio Castellucci, Roberto Saletti: Designing Carry Look-Ahead Adders with an Adiabatic Logic Standard-Cell Library. PATMOS 2002: 118-127
2001
4	EE	Luca Fanucci, Roberto Roncella, Roberto Saletti: Non-linearity reduction technique for delay-locked delay-lines. ISCAS (4) 2001: 430-433
1999
3	EE	Fernando De Bernardinis, Roberto Roncella, Roberto Saletti, Pierangelo Terreni, Graziano Bertini: An efficient VLSI architecture for real-time additive synthesis of musical signals. IEEE Trans. VLSI Syst. 7(1): 105-110 (1999)
1997
2	EE	Riccardo Mariani, Roberto Roncella, Roberto Saletti, Pierangelo Terreni: On the Realisation of Delay-Insensitive Asynchronous Circuits with CMOS Ternary Logic. ASYNC 1997: 54-
1	EE	Riccardo Mariani, Roberto Roncella, Roberto Saletti, Pierangelo Terreni: Useful Application of CMOS Ternary Logic to the Realisation of Asynchronous Circuits. ISMVL 1997: 203-208

Coauthor Index

1	D. Audino	[14]
2	F. Baronti	[11] [12] [13] [14]
3	Fernando De Bernardinis	[3]
4	Graziano Bertini	[3]
5	Fabrizio Bertuccelli	[8] [10]
6	Franco Bigongiari	[6] [8] [10]
7	Antonio Blotti	[5] [9]
8	G. Bonfini	[7]
9	Andrea S. Brogna	[6] [8] [10]
10	Maurizio Castellucci	[5]
11	Silvia Chiusano	[6]
12	P. D'Abramo	[11] [12]
13	Walter Errico	[10]
14	H. Fabian	[12]
15	Luca Fanucci	[4]
16	C. Garbossa	[7]
17	M. Giardi	[12]
18	Simone Giovannetti	[10]
19	M. Knaipp	[11]
20	A. Lazzeri	[14]
21	F. Lenzi	[13]
22	Riccardo Mariani	[1] [2]
23	R. Minixhofer	[11]
24	Giorgio Di Natale	[8]
25	Egidio Pescari	[10]
26	L. Di Piro	[12]
27	Paolo Prinetto	[6] [8]
28	Roberto Roncella	[1] [2] [3] [4] [11] [12] [13] [14]
29	M. Schrems	[11]
30	R. Serventi	[11]
31	Pierangelo Terreni	[1] [2] [3]
32	V. Vescoli	[11]

Colors in the list of coauthors