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Roberto Saletti

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2007
14EED. Audino, F. Baronti, A. Lazzeri, Roberto Roncella, Roberto Saletti: FPGA/DSP-based Configurable Multi-Channel Counter. DSD 2007: 376-382
13EEF. Baronti, F. Lenzi, Roberto Roncella, Roberto Saletti: A Hardware-Software Platform for Design and Verification of In-Motorcycle Electronic Systems. DSD 2007: 440-443
12EEF. Baronti, Roberto Roncella, Roberto Saletti, P. D'Abramo, L. Di Piro, H. Fabian, M. Giardi: The importance of At-Speed Scan Testing: an industrial experience. DSD 2007: 672-675
2006
11EEF. Baronti, P. D'Abramo, M. Knaipp, R. Minixhofer, Roberto Roncella, Roberto Saletti, M. Schrems, R. Serventi, V. Vescoli: FlexRay transceiver in a 0.35 µm CMOS high-voltage technology. DATE Designers' Forum 2006: 201-205
2004
10EEAndrea S. Brogna, Franco Bigongiari, Fabrizio Bertuccelli, Walter Errico, Simone Giovannetti, Egidio Pescari, Roberto Saletti: SEU Protected CPU for Slow Control on Space Vehicles. DELTA 2004: 422-424
9EEAntonio Blotti, Roberto Saletti: Ultralow-power adiabatic circuit semi-custom design. IEEE Trans. VLSI Syst. 12(11): 1248-1253 (2004)
2003
8EEFabrizio Bertuccelli, Franco Bigongiari, Andrea S. Brogna, Giorgio Di Natale, Paolo Prinetto, Roberto Saletti: Exhaustive Test of Several Dependable Memory Architectures Designed by GRAAL Tool. Asian Test Symposium 2003: 32-37
7 G. Bonfini, C. Garbossa, Roberto Saletti: A Switched Opamp-based 10-b Integrated ADC for Ultra Low-power Applications. VLSI-SOC 2003: 136-141
6 Andrea S. Brogna, Franco Bigongiari, Silvia Chiusano, Paolo Prinetto, Roberto Saletti: Designing and Testing High Dependable Memories for Aerospace Applications. VLSI-SOC 2003: 221-
2002
5EEAntonio Blotti, Maurizio Castellucci, Roberto Saletti: Designing Carry Look-Ahead Adders with an Adiabatic Logic Standard-Cell Library. PATMOS 2002: 118-127
2001
4EELuca Fanucci, Roberto Roncella, Roberto Saletti: Non-linearity reduction technique for delay-locked delay-lines. ISCAS (4) 2001: 430-433
1999
3EEFernando De Bernardinis, Roberto Roncella, Roberto Saletti, Pierangelo Terreni, Graziano Bertini: An efficient VLSI architecture for real-time additive synthesis of musical signals. IEEE Trans. VLSI Syst. 7(1): 105-110 (1999)
1997
2EERiccardo Mariani, Roberto Roncella, Roberto Saletti, Pierangelo Terreni: On the Realisation of Delay-Insensitive Asynchronous Circuits with CMOS Ternary Logic. ASYNC 1997: 54-
1EERiccardo Mariani, Roberto Roncella, Roberto Saletti, Pierangelo Terreni: Useful Application of CMOS Ternary Logic to the Realisation of Asynchronous Circuits. ISMVL 1997: 203-208

Coauthor Index

1D. Audino [14]
2F. Baronti [11] [12] [13] [14]
3Fernando De Bernardinis [3]
4Graziano Bertini [3]
5Fabrizio Bertuccelli [8] [10]
6Franco Bigongiari [6] [8] [10]
7Antonio Blotti [5] [9]
8G. Bonfini [7]
9Andrea S. Brogna [6] [8] [10]
10Maurizio Castellucci [5]
11Silvia Chiusano [6]
12P. D'Abramo [11] [12]
13Walter Errico [10]
14H. Fabian [12]
15Luca Fanucci [4]
16C. Garbossa [7]
17M. Giardi [12]
18Simone Giovannetti [10]
19M. Knaipp [11]
20A. Lazzeri [14]
21F. Lenzi [13]
22Riccardo Mariani [1] [2]
23R. Minixhofer [11]
24Giorgio Di Natale [8]
25Egidio Pescari [10]
26L. Di Piro [12]
27Paolo Prinetto [6] [8]
28Roberto Roncella [1] [2] [3] [4] [11] [12] [13] [14]
29M. Schrems [11]
30R. Serventi [11]
31Pierangelo Terreni [1] [2] [3]
32V. Vescoli [11]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)