Denis Flandre

2008
16	EE	David Bol, Renaud Ambroise, Denis Flandre, Jean-Didier Legat: Analysis and minimization of practical energy in 45nm subthreshold logic circuits. ICCD 2008: 294-300
15	EE	Ahmed El Oualkadi, Denis Flandre: Systematic HDL Design of a Delta-Sigma Fractional-N Phase-Locked Loop for Wireless Applications. ISVLSI 2008: 173-178
14	EE	David Bol, Renaud Ambroise, Denis Flandre, Jean-Didier Legat: Impact of Technology Scaling on Digital Subthreshold Circuits. ISVLSI 2008: 179-184
2007
13	EE	Ilham Hassoune, François Macé, Denis Flandre, Jean-Didier Legat: Dynamic differential self-timed logic families for robust and low-power security ICs. Integration 40(3): 355-364 (2007)
12	EE	Joaquín Alvarado, Antonio Cerdeira, Valeria Kilchytska, Denis Flandre: Harmonic distortion analysis using an improved charge sheet model for PD SOI MOSFETs. Microelectronics Journal 38(3): 321-326 (2007)
2006
11	EE	Salvador Pinillos Gimenez, Marcelo Antonio Pavanello, João Antonio Martino, Denis Flandre: Gain improvement in operational transconductance amplifiers using Graded-Channel SOI nMOSFETS. Microelectronics Journal 37(1): 31-37 (2006)
10	EE	Marcelo Antonio Pavanello, Paula Ghedini Der Agopian, João Antonio Martino, Denis Flandre: Cryogenic operation of graded-channel silicon-on-insulator nMOSFETs for high performance analog applications. Microelectronics Journal 37(2): 137-144 (2006)
9	EE	Ilham Hassoune, François Macé, Denis Flandre, Jean-Didier Legat: Low-swing current mode logic (LSCML): A new logic style for secure and robust smart cards against power analysis attacks. Microelectronics Journal 37(9): 997-1006 (2006)
2005
8	EE	David Levacq, Vincent Dessard, Denis Flandre: Ultra-low power flip-flops for MTCMOS circuits. ISCAS (5) 2005: 4681-4684
2004
7	EE	Ilham Hassoune, Amaury Nève, Jean-Didier Legat, Denis Flandre: Investigation of Low-Power Low-Voltage Circuit Techniques for a Hybrid Full-Adder Cell. PATMOS 2004: 189-197
6		Amaury Nève, Helmut Schettler, Thomas Ludwig, Denis Flandre: Power-delay product minimization in high-performance 64-bit carry-select adders. IEEE Trans. VLSI Syst. 12(3): 235-244 (2004)
2003
5	EE	Salvador Pinillos Gimenez, Marcelo Antonio Pavanello, João Antonio Martino, S. Adriaensen, Denis Flandre: Design of Operational Transconductance Amplifiers with Improved Gain by Using Graded-Channel SOI nMOSFETs. SBCCI 2003: 26-
4	EE	Amaury Nève, Denis Flandre, Jean-Jacques Quisquater: SOI Technology for Future High-Performance Smart Cards. IEEE Micro 23(3): 58-67 (2003)
3	EE	Magali Estrada, A. Afzalian, Denis Flandre, Antonio Cerdeira, H. Baez, A. de Lucca: FD MOS SOI circuit to enhance the ratio of illuminated to dark current of a co-integrated a-Si: H photodiode. Microelectronics Reliability 43(2): 189-193 (2003)
2002
2	EE	Amaury Nève, Denis Flandre, Helmut Schettler, Thomas Ludwig, Gerhard Hellner: Design of a branch-based 64-bit carry-select adder in 0.18 µm partially depleted SOI CMOS. ISLPED 2002: 108-111
2001
1		Amaury Nève, Denis Flandre: Design of a Branch-Based Carry-Select Adder IP Portable in 0.25 µm Bulk and Silicon-On-Insulator CMOS Technologies. VLSI-SOC 2001: 169-180

Coauthor Index

1	S. Adriaensen	[5]
2	A. Afzalian	[3]
3	Paula Ghedini Der Agopian	[10]
4	Joaquín Alvarado	[12]
5	Renaud Ambroise	[14] [16]
6	H. Baez	[3]
7	David Bol	[14] [16]
8	Antonio Cerdeira	[3] [12]
9	Vincent Dessard	[8]
10	Magali Estrada	[3]
11	Salvador Pinillos Gimenez	[5] [11]
12	Ilham Hassoune	[7] [9] [13]
13	Gerhard Hellner	[2]
14	Valeria Kilchytska	[12]
15	Jean-Didier Legat	[7] [9] [13] [14] [16]
16	David Levacq	[8]
17	A. de Lucca	[3]
18	Thomas Ludwig	[2] [6]
19	François Macé	[9] [13]
20	João Antonio Martino	[5] [10] [11]
21	Amaury Nève	[1] [2] [4] [6] [7]
22	Ahmed El Oualkadi	[15]
23	Marcelo Antonio Pavanello	[5] [10] [11]
24	Jean-Jacques Quisquater	[4]
25	Helmut Schettler	[2] [6]

Colors in the list of coauthors