Aristides Efthymiou

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15EEDilip P. Vasudevan, Aristides Efthymiou: A Partial Scan Based Test Generation for Asynchronous Circuits. DDECS 2008: 186-189
14EERahman Hassan, Antony Harris, Nigel P. Topham, Aristides Efthymiou: Synthetic Trace-Driven Simulation of Cache Memory. AINA Workshops (1) 2007: 764-771
13 Aristides Efthymiou: Redundancy and Test-Pattern Generation for Asynchronous Quasi-Delay-Insensitive Combinational Circuits. DDECS 2007: 377-382
12EEAristides Efthymiou, Jim D. Garside, Ioannis Papaefstathiou: A Low-Power Processor Architecture Optimized forWireless Devices. ASAP 2005: 185-190
11EESotirios Matakias, Y. Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, Aristides Efthymiou: Fast, Parallel Two-Rail Code Checker with Enhanced Testability. IOLTS 2005: 149-156
10EEAristides Efthymiou, John Bainbridge, Douglas A. Edwards: Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect. IEEE Trans. VLSI Syst. 13(12): 1384-1393 (2005)
9EEAristides Efthymiou, W. Suntiamorntut, Jim D. Garside, L. E. M. Brackenbury: An Asynchronous, Iterative Implementation of the Original Booth Multiplication Algorithm. ASYNC 2004: 207-215
8EEAristides Efthymiou, John Bainbridge, Douglas A. Edwards: Adding Testability to an Asynchronous Interconnect for GALS SoC. Asian Test Symposium 2004: 20-23
7EEAristides Efthymiou, Christos P. Sotiriou, Douglas A. Edwards: Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits. DATE 2004: 672-673
6 Aristides Efthymiou, Jim D. Garside: A CAM with mixed serial-parallel comparison for use in low energy caches. IEEE Trans. VLSI Syst. 12(3): 325-329 (2004)
5EEAristides Efthymiou, Jim D. Garside: Adaptive Pipeline Structures fo Speculation Control. ASYNC 2003: 46-55
4EEAristides Efthymiou, Jim D. Garside: Adaptive Pipeline Depth Control for Processor Power-Management. ICCD 2002: 454-457
3EEAristides Efthymiou, Jim D. Garside: An adaptive serial-parallel CAM architecture for low-power cache blocks. ISLPED 2002: 136-141
2EEStephen B. Furber, Aristides Efthymiou, Jim D. Garside, David W. Lloyd, Mike J. G. Lewis, Steve Temple: Power Management in the Amulet Microprocessors. IEEE Design & Test of Computers 18(2): 42-52 (2001)
1EEManolis Katevenis, Panagiota Vatsolaki, Aristides Efthymiou: Pipelined Memory Shared Buffer for VLSI Switches. SIGCOMM 1995: 39-48

Coauthor Index

1Angela Arapoyanni (Aggeliki Arapoyanni) [11]
2John Bainbridge [8] [10]
3L. E. M. Brackenbury [9]
4Douglas A. Edwards [7] [8] [10]
5Stephen B. Furber (Steve Furber) [2]
6Jim D. Garside [2] [3] [4] [5] [6] [9] [12]
7Themistoklis Haniotakis (Th. Haniotakis) [11]
8Antony Harris [14]
9Rahman Hassan [14]
10Manolis Katevenis [1]
11Mike J. G. Lewis [2]
12David W. Lloyd [2]
13Sotirios Matakias [11]
14Ioannis Papaefstathiou [12]
15Christos P. Sotiriou [7]
16W. Suntiamorntut [9]
17Steve Temple [2]
18Nigel P. Topham [14]
19Yiorgos Tsiatouhas (Y. Tsiatouhas) [11]
20Dilip P. Vasudevan [15]
21Panagiota Vatsolaki [1]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)