Aristides Efthymiou

2008
15	EE	Dilip P. Vasudevan, Aristides Efthymiou: A Partial Scan Based Test Generation for Asynchronous Circuits. DDECS 2008: 186-189
2007
14	EE	Rahman Hassan, Antony Harris, Nigel P. Topham, Aristides Efthymiou: Synthetic Trace-Driven Simulation of Cache Memory. AINA Workshops (1) 2007: 764-771
13		Aristides Efthymiou: Redundancy and Test-Pattern Generation for Asynchronous Quasi-Delay-Insensitive Combinational Circuits. DDECS 2007: 377-382
2005
12	EE	Aristides Efthymiou, Jim D. Garside, Ioannis Papaefstathiou: A Low-Power Processor Architecture Optimized forWireless Devices. ASAP 2005: 185-190
11	EE	Sotirios Matakias, Y. Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, Aristides Efthymiou: Fast, Parallel Two-Rail Code Checker with Enhanced Testability. IOLTS 2005: 149-156
10	EE	Aristides Efthymiou, John Bainbridge, Douglas A. Edwards: Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect. IEEE Trans. VLSI Syst. 13(12): 1384-1393 (2005)
2004
9	EE	Aristides Efthymiou, W. Suntiamorntut, Jim D. Garside, L. E. M. Brackenbury: An Asynchronous, Iterative Implementation of the Original Booth Multiplication Algorithm. ASYNC 2004: 207-215
8	EE	Aristides Efthymiou, John Bainbridge, Douglas A. Edwards: Adding Testability to an Asynchronous Interconnect for GALS SoC. Asian Test Symposium 2004: 20-23
7	EE	Aristides Efthymiou, Christos P. Sotiriou, Douglas A. Edwards: Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits. DATE 2004: 672-673
6		Aristides Efthymiou, Jim D. Garside: A CAM with mixed serial-parallel comparison for use in low energy caches. IEEE Trans. VLSI Syst. 12(3): 325-329 (2004)
2003
5	EE	Aristides Efthymiou, Jim D. Garside: Adaptive Pipeline Structures fo Speculation Control. ASYNC 2003: 46-55
2002
4	EE	Aristides Efthymiou, Jim D. Garside: Adaptive Pipeline Depth Control for Processor Power-Management. ICCD 2002: 454-457
3	EE	Aristides Efthymiou, Jim D. Garside: An adaptive serial-parallel CAM architecture for low-power cache blocks. ISLPED 2002: 136-141
2001
2	EE	Stephen B. Furber, Aristides Efthymiou, Jim D. Garside, David W. Lloyd, Mike J. G. Lewis, Steve Temple: Power Management in the Amulet Microprocessors. IEEE Design & Test of Computers 18(2): 42-52 (2001)
1995
1	EE	Manolis Katevenis, Panagiota Vatsolaki, Aristides Efthymiou: Pipelined Memory Shared Buffer for VLSI Switches. SIGCOMM 1995: 39-48

Coauthor Index

1	Angela Arapoyanni (Aggeliki Arapoyanni)	[11]
2	John Bainbridge	[8] [10]
3	L. E. M. Brackenbury	[9]
4	Douglas A. Edwards	[7] [8] [10]
5	Stephen B. Furber (Steve Furber)	[2]
6	Jim D. Garside	[2] [3] [4] [5] [6] [9] [12]
7	Themistoklis Haniotakis (Th. Haniotakis)	[11]
8	Antony Harris	[14]
9	Rahman Hassan	[14]
10	Manolis Katevenis	[1]
11	Mike J. G. Lewis	[2]
12	David W. Lloyd	[2]
13	Sotirios Matakias	[11]
14	Ioannis Papaefstathiou	[12]
15	Christos P. Sotiriou	[7]
16	W. Suntiamorntut	[9]
17	Steve Temple	[2]
18	Nigel P. Topham	[14]
19	Yiorgos Tsiatouhas (Y. Tsiatouhas)	[11]
20	Dilip P. Vasudevan	[15]
21	Panagiota Vatsolaki	[1]

Colors in the list of coauthors