Akashi Satoh

2008
32	EE	Akashi Satoh, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki: High-Performance Concurrent Error Detection Scheme for AES Hardware. CHES 2008: 100-112
31	EE	Naofumi Homma, Atsushi Miyamoto, Takafumi Aoki, Akashi Satoh, Adi Shamir: Collision-Based Power Analysis of Modular Exponentiation Using Chosen-Message Pairs. CHES 2008: 15-29
30	EE	Yohei Hori, Akashi Satoh, Hirofumi Sakane, Kenji Toda: Bitstream encryption and authentication with AES-GCM in dynamically reconfigurable systems. FPL 2008: 23-28
29	EE	Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh: Chosen-message SPA attacks against FPGA-based RSA hardware implementations. FPL 2008: 35-40
28	EE	Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh: Systematic design of high-radix Montgomery multipliers for RSA processors. ICCD 2008: 416-421
27	EE	Akashi Satoh: ASIC hardware implementations for 512-bit hash function Whirlpool. ISCAS 2008: 2917-2920
26	EE	Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh: High-performance ASIC implementations of the 128-bit block cipher CLEFIA. ISCAS 2008: 2925-2928
25	EE	Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh: Enhanced power analysis attack using chosen message against RSA hardware implementations. ISCAS 2008: 3282-3285
24	EE	Yohei Hori, Akashi Satoh, Hirofumi Sakane, Kenji Toda: Bitstream Encryption and Authentication Using AES-GCM in Dynamically Reconfigurable Systems. IWSEC 2008: 261-278
23	EE	Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh: Compact ASIC Architectures for the 512-Bit Hash Function Whirlpool. WISA 2008: 28-40
22	EE	Naofumi Homma, Sei Nagashima, Takeshi Sugawara, Takafumi Aoki, Akashi Satoh: A High-Resolution Phase-Based Waveform Matching and Its Application to Side-Channel Attacks. IEICE Transactions 91-A(1): 193-202 (2008)
2007
21	EE	Akashi Satoh, Takeshi Sugawara, Takafumi Aoki: High-Speed Pipelined Hardware Architecture for Galois Counter Mode. ISC 2007: 118-129
20	EE	Sei Nagashima, Naofumi Homma, Yuichi Imai, Takafumi Aoki, Akashi Satoh: DPA Using Phase-Based Waveform Matching against Random-Delay Countermeasure. ISCAS 2007: 1807-1810
19	EE	Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh: SPA against an FPGA-Based RSA Implementation with a High-Radix Montgomery Multiplier. ISCAS 2007: 1847-1850
18	EE	Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh: A High-Performance ASIC Implementation of the 64-bit Block Cipher CAST-128. ISCAS 2007: 1859-1862
17	EE	Akashi Satoh: High-Speed Parallel Hardware Architecture for Galois Counter Mode. ISCAS 2007: 1863-1866
16	EE	Akashi Satoh, Tadanobu Inoue: ASIC-hardware-focused comparison for hash functions MD5, RIPEMD-160, and SHS. Integration 40(1): 3-10 (2007)
2006
15	EE	Naofumi Homma, Sei Nagashima, Yuichi Imai, Takafumi Aoki, Akashi Satoh: High-Resolution Side-Channel Attack Using Phase-Based Waveform Matching. CHES 2006: 187-200
2005
14	EE	Akashi Satoh: Hardware Architecture and Cost Estimates for Breaking SHA-1. ISC 2005: 259-273
13	EE	Akashi Satoh, Tadanobu Inoue: ASIC-Hardware-Focused Comparison for Hash Functions MD5, RIPEMD-160, and SHS. ITCC (1) 2005: 532-537
2004
12	EE	Shigenori Shimizu, Hiroshi Ishikawa, Akashi Satoh, Toru Aihara: On-demand design service innovations. IBM Journal of Research and Development 48(5-6): 751-766 (2004)
11	EE	Sumio Morioka, Akashi Satoh: A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture. IEEE Trans. VLSI Syst. 12(7): 686-691 (2004)
2003
10	EE	Akashi Satoh, Sumio Morioka: Unified Hardware Architecture for 128-Bit Block Ciphers AES and Camellia. CHES 2003: 304-318
9	EE	Akashi Satoh, Sumio Morioka: Hardware-Focused Performance Comparison for the Standard Block Ciphers AES, Camellia, and Triple-DES. ISC 2003: 252-266
8	EE	Akashi Satoh, Kohji Takano: A Scalable Dual-Field Elliptic Curve Cryptographic Processor. IEEE Trans. Computers 52(4): 449-460 (2003)
2002
7	EE	Sumio Morioka, Akashi Satoh: An Optimized S-Box Circuit Architecture for Low Power AES Design. CHES 2002: 172-186
6	EE	Sumio Morioka, Akashi Satoh: A 10 Gbps Full-AES Crypto Design with a Twisted-BDD S-Box Architecture. ICCD 2002: 98-103
5	EE	Akashi Satoh, Sumio Morioka: Small and High-Speed Hardware Architectures for the 3GPP Standard Cipher KASUMI. ISC 2002: 48-62
2001
4	EE	Akashi Satoh, Sumio Morioka, Kohji Takano, Seiji Munetoh: A Compact Rijndael Hardware Architecture with S-Box Optimization. ASIACRYPT 2001: 239-254
2000
3		Akashi Satoh, Nobuyuki Ooba, Kohji Takano, Edward D'Avignon: High-Speed MARS Hardware. AES Candidate Conference 2000: 305-316
1997
2		W. K. Luk, Y. Katayama, Wei Hwang, Matthew R. Wordeman, T. Kirihata, Akashi Satoh, Seiji Munetoh, H. Wong, B. El-Kareh, P. Xiao, Rajiv V. Joshi: Development of a High Bandwidth Merged Logic/DRAM Multimedia Chip. ICCD 1997: 279-285
1		Akashi Satoh, Y. Kobayashi, H. Niijima, Nobuyuki Ooba, Seiji Munetoh, S. Sone: A High-Speed Small RSA Encryption LSI with Low Power Dissipation. ISW 1997: 174-187

Coauthor Index

1	Toru Aihara	[12]
2	Takafumi Aoki	[15] [18] [19] [20] [21] [22] [23] [25] [26] [28] [29] [31] [32]
3	Edward D'Avignon	[3]
4	B. El-Kareh	[2]
5	Naofumi Homma	[15] [18] [19] [20] [22] [23] [25] [26] [28] [29] [31] [32]
6	Yohei Hori	[24] [30]
7	Wei Hwang	[2]
8	Yuichi Imai	[15] [20]
9	Tadanobu Inoue	[13] [16]
10	Hiroshi Ishikawa	[12]
11	Rajiv V. Joshi	[2]
12	Y. Katayama	[2]
13	T. Kirihata	[2]
14	Y. Kobayashi	[1]
15	W. K. Luk	[2]
16	Atsushi Miyamoto	[19] [25] [28] [29] [31]
17	Sumio Morioka	[4] [5] [6] [7] [9] [10] [11]
18	Seiji Munetoh	[1] [2] [4]
19	Sei Nagashima	[15] [20] [22]
20	H. Niijima	[1]
21	Nobuyuki Ooba	[1] [3]
22	Hirofumi Sakane	[24] [30]
23	Adi Shamir	[31]
24	Shigenori Shimizu	[12]
25	S. Sone	[1]
26	Takeshi Sugawara	[18] [21] [22] [23] [26] [32]
27	Kohji Takano	[3] [4] [8]
28	Kenji Toda	[24] [30]
29	H. Wong	[2]
30	Matthew R. Wordeman	[2]
31	P. Xiao	[2]

Colors in the list of coauthors