| 2004 |
|---|
| 13 | EE | Sumio Morioka,
Akashi Satoh:
A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture.
IEEE Trans. VLSI Syst. 12(7): 686-691 (2004) |
| 2003 |
|---|
| 12 | EE | Akashi Satoh,
Sumio Morioka:
Unified Hardware Architecture for 128-Bit Block Ciphers AES and Camellia.
CHES 2003: 304-318 |
| 11 | EE | Akashi Satoh,
Sumio Morioka:
Hardware-Focused Performance Comparison for the Standard Block Ciphers AES, Camellia, and Triple-DES.
ISC 2003: 252-266 |
| 2002 |
|---|
| 10 | EE | Sumio Morioka,
Akashi Satoh:
An Optimized S-Box Circuit Architecture for Low Power AES Design.
CHES 2002: 172-186 |
| 9 | EE | Sumio Morioka,
Akashi Satoh:
A 10 Gbps Full-AES Crypto Design with a Twisted-BDD S-Box Architecture.
ICCD 2002: 98-103 |
| 8 | EE | Akashi Satoh,
Sumio Morioka:
Small and High-Speed Hardware Architectures for the 3GPP Standard Cipher KASUMI.
ISC 2002: 48-62 |
| 2001 |
|---|
| 7 | EE | Akashi Satoh,
Sumio Morioka,
Kohji Takano,
Seiji Munetoh:
A Compact Rijndael Hardware Architecture with S-Box Optimization.
ASIACRYPT 2001: 239-254 |
| 6 | EE | Sumio Morioka,
Yasunao Katayama,
Toshiyuki Yamane:
Towards Efficient Verification of Arithmetic Algorithms over Galois Fields GF(2m).
CAV 2001: 465-477 |
| 2000 |
|---|
| 5 | EE | Yasunao Katayama,
Yasushi Negishi,
Sumio Morioka:
Efficient Error Correction Code Configurations for Quasi-Nonvolatile Data Retention by DRAMs.
DFT 2000: 201- |
| 4 | EE | Yasunao Katayama,
Sumio Morioka:
One-Shot Reed-Solomon Decoding for High-Performance Dependable Systems.
DSN 2000: 390- |
| 1999 |
|---|
| 3 | EE | Yasunao Katayama,
Eric J. Stuckey,
Sumio Morioka,
Zhao Wu:
Fault-Tolerant Refresh Power Reduction of DRAMs for Quasi-Nonvolatile Data Retention.
DFT 1999: 311-318 |
| 2 | EE | Sumio Morioka,
Yasunao Katayama:
Design Methodology for a One-Shot Reed-Solomon Encoder and Decoder.
ICCD 1999: 60-67 |
| 1994 |
|---|
| 1 | | Junji Kitamichi,
Sumio Morioka,
Teruo Higashino,
Kenichi Taniguchi:
Automatic Correctness Proof of the Implementation of Synchronous Sequential Circuits Using an Algebraic Approach.
TPCD 1994: 165-184 |
