Nam Sung Kim

2008
17	EE	David Roberts, Nam Sung Kim, Trevor N. Mudge: On-chip cache device scaling limits and effective fault repair techniques in future nanoscale technology. Microprocessors and Microsystems - Embedded Hardware Design 32(5-6): 244-253 (2008)
2007
16	EE	David Roberts, Nam Sung Kim, Trevor N. Mudge: On-Chip Cache Device Scaling Limits and Effective Fault Repair Techniques in Future Nanoscale Technology. DSD 2007: 570-578
15	EE	Gregory K. Chen, David Blaauw, Trevor N. Mudge, Dennis Sylvester, Nam Sung Kim: Yield-driven near-threshold SRAM design. ICCAD 2007: 660-666
14	EE	Robert Bai, Nam Sung Kim, Taeho Kgil, Dennis Sylvester, Trevor N. Mudge: Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage CoRR abs/0710.4794: (2007)
2005
13	EE	Robert Bai, Nam Sung Kim, Dennis Sylvester, Trevor N. Mudge: Total leakage optimization strategies for multi-level caches. ACM Great Lakes Symposium on VLSI 2005: 381-384
12	EE	Robert Bai, Nam Sung Kim, Taeho Kgil, Dennis Sylvester, Trevor N. Mudge: Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage. DATE 2005: 650-651
11	EE	Nam Sung Kim, David Blaauw, Trevor N. Mudge: Quantitative analysis and optimization techniques for on-chip cache leakage power. IEEE Trans. VLSI Syst. 13(10): 1147-1156 (2005)
2004
10	EE	Nam Sung Kim, Taeho Kgil, Valeria Bertacco, Todd M. Austin, Trevor N. Mudge: Microarchitectural power modeling techniques for deep sub-micron microprocessors. ISLPED 2004: 212-217
9	EE	Dan Ernst, Shidhartha Das, Seokwoo Lee, David Blaauw, Todd M. Austin, Trevor N. Mudge, Nam Sung Kim, Krisztián Flautner: Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation. IEEE Micro 24(6): 10-20 (2004)
8		Nam Sung Kim, Krisztián Flautner, David Blaauw, Trevor N. Mudge: Circuit and microarchitectural techniques for reducing cache leakage power. IEEE Trans. VLSI Syst. 12(2): 167-184 (2004)
2003
7	EE	Nam Sung Kim, David Blaauw, Trevor N. Mudge: Leakage Power Optimization Techniques for Ultra Deep Sub-Micron Multi-Level Caches. ICCAD 2003: 627-632
6	EE	Nam Sung Kim, Trevor N. Mudge: Reducing register ports using delayed write-back queues and operand pre-fetch. ICS 2003: 172-182
5	EE	Nam Sung Kim, Trevor N. Mudge: The microarchitecture of a low power register file. ISLPED 2003: 384-389
4	EE	Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Rajeev R. Rao, Toan Pham, Conrad H. Ziesler, David Blaauw, Todd M. Austin, Krisztián Flautner, Trevor N. Mudge: Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation. MICRO 2003: 7-18
3	EE	Nam Sung Kim, Todd M. Austin, David Blaauw, Trevor N. Mudge, Krisztián Flautner, Jie S. Hu, Mary Jane Irwin, Mahmut T. Kandemir, Narayanan Vijaykrishnan: Leakage Current: Moore's Law Meets Static Power. IEEE Computer 36(12): 68-75 (2003)
2002
2	EE	Krisztián Flautner, Nam Sung Kim, Steven M. Martin, David Blaauw, Trevor N. Mudge: Drowsy Caches: Simple Techniques for Reducing Leakage Power. ISCA 2002: 148-157
1	EE	Nam Sung Kim, Krisztián Flautner, David Blaauw, Trevor N. Mudge: Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction. MICRO 2002: 219-230

Coauthor Index

1	Todd M. Austin	[3] [4] [9] [10]
2	Robert Bai	[12] [13] [14]
3	Valeria Bertacco	[10]
4	David Blaauw (David T. Blaauw)	[1] [2] [3] [4] [7] [8] [9] [11] [15]
5	Gregory K. Chen	[15]
6	Shidhartha Das	[4] [9]
7	Dan Ernst	[4] [9]
8	Krisztián Flautner	[1] [2] [3] [4] [8] [9]
9	Jie S. Hu	[3]
10	Mary Jane Irwin	[3]
11	Mahmut T. Kandemir	[3]
12	Taeho Kgil	[10] [12] [14]
13	Seokwoo Lee	[9]
14	Steven M. Martin	[2]
15	Trevor N. Mudge	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17]
16	Sanjay Pant	[4]
17	Toan Pham	[4]
18	Rajeev R. Rao	[4]
19	David Roberts	[16] [17]
20	Dennis Sylvester	[12] [13] [14] [15]
21	Narayanan Vijaykrishnan (Vijaykrishnan Narayanan)	[3]
22	Conrad H. Ziesler	[4]