2003 |
25 | EE | Pak K. Chan,
Martine D. F. Schlag:
Parallel placement for field-programmable gate arrays.
FPGA 2003: 43-50 |
2000 |
24 | EE | Pak K. Chan,
Martine D. F. Schlag:
New parallelization and convergence results for NC: a negotiation-based FPGA router.
FPGA 2000: 165-174 |
23 | EE | Pak K. Chan,
Martine D. F. Schlag,
Carl Ebeling,
Larry McMurchie:
Distributed-memory parallel routing for field-programmable gatearrays.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(8): 850-862 (2000) |
1999 |
22 | EE | Jason Y. Zien,
Martine D. F. Schlag,
Pak K. Chan:
Multilevel spectral hypergraph partitioning with arbitrary vertex sizes.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(9): 1389-1399 (1999) |
1997 |
21 | EE | Pak K. Chan,
Martine D. F. Schlag:
Acceleration of an FPGA router.
FCCM 1997: 175-181 |
20 | EE | Jason Y. Zien,
Pak K. Chan,
Martine D. F. Schlag:
Hybrid spectral/iterative partitioning.
ICCAD 1997: 436-440 |
1996 |
19 | EE | Jason Y. Zien,
Martine D. F. Schlag,
Pak K. Chan:
Multi-level spectral hypergraph partitioning with arbitrary vertex sizes.
ICCAD 1996: 201-204 |
18 | | Martine D. F. Schlag,
F. Joel Ferguson:
Detection of Multiple Faults in Two-Dimensional ILAs.
IEEE Trans. Computers 45(6): 741-746 (1996) |
17 | EE | Pak K. Chan,
Martine D. F. Schlag,
Jason Y. Zien:
Spectral-based multiway FPGA partitioning.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(5): 554-560 (1996) |
1995 |
16 | EE | Pak K. Chan,
Martine D. F. Schlag,
Jason Y. Zien:
Spectral-Based Multi-Way FPGA Partitioning.
FPGA 1995: 133-139 |
1994 |
15 | EE | Martine D. F. Schlag,
Jackson Kong,
Pak K. Chan:
Routability-driven technology mapping for lookup table-based FPGA's.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(1): 13-26 (1994) |
14 | EE | Pak K. Chan,
Martine D. F. Schlag,
Jason Y. Zien:
Spectral K-way ratio-cut partitioning and clustering.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(9): 1088-1096 (1994) |
1993 |
13 | EE | Pak K. Chan,
Martine D. F. Schlag,
Jason Y. Zien:
On Routability Prediction for Field-Programmable Gate Arrays.
DAC 1993: 326-330 |
12 | EE | Pak K. Chan,
Martine D. F. Schlag,
Jason Y. Zien:
Spectral K-Way Ratio-Cut Partitioning and Clustering.
DAC 1993: 749-754 |
11 | | Richard Anderson,
Simon Kahan,
Martine D. F. Schlag:
Single-Layer Cylindrical Compaction.
Algorithmica 9(3): 293-312 (1993) |
10 | EE | Martine D. F. Schlag,
Pak K. Chan,
Jackson Kong:
Empirical evaluation of multilevel logic minimization tools for a lookup-table-based field-programmable gate array technology.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(5): 713-722 (1993) |
1992 |
9 | | Martine D. F. Schlag,
Jackson Kong,
Pak K. Chan:
Routability-Driven Techology Mapping for LookUp-Table-Based FPGAs.
ICCD 1992: 86-90 |
8 | | Pak K. Chan,
Martine D. F. Schlag,
Clark D. Thomborson,
Vojin G. Oklobdzija:
Delay Optimization of Carry-Skip Adders and Block Carry-Lookahead Adders Using Multidimensional Dynamic Programming.
IEEE Trans. Computers 41(8): 920-930 (1992) |
1990 |
7 | | Pak K. Chan,
Martine D. F. Schlag:
Analysis and Design of CMOS Manchester Adders with Variable Carry-Skip.
IEEE Trans. Computers 39(8): 983-992 (1990) |
1989 |
6 | | Richard Anderson,
Simon Kahan,
Martine D. F. Schlag:
An O(n log n) Algorithm for 1-D Tile Compaction.
WG 1989: 287-301 |
5 | EE | Pak K. Chan,
Martine D. F. Schlag:
Bounds on signal delay in RC mesh networks.
IEEE Trans. on CAD of Integrated Circuits and Systems 8(6): 581-589 (1989) |
1987 |
4 | | Martine D. F. Schlag:
The planar topology of functional programs.
FPCA 1987: 174-193 |
3 | | Ying-Fung Wu,
Peter Widmayer,
Martine D. F. Schlag,
C. K. Wong:
Rectilinear Shortest Paths and Minimum Spanning Trees in the Presence of Rectilinear Obstacles.
IEEE Trans. Computers 36(3): 321-331 (1987) |
1985 |
2 | | Dorab Patel,
Martine D. F. Schlag,
Milos D. Ercegovac:
vFP: An Environment for the Multi-level Specification, Analysis, and Synthesis of Hardware Algorithms.
FPCA 1985: 238-255 |
1 | EE | Martine D. F. Schlag,
Ellen J. Yoffa,
Peter S. Hauge,
Chak-Kuen Wong:
A Method for Improving Cascode-Switch Macro Wirability.
IEEE Trans. on CAD of Integrated Circuits and Systems 4(2): 150-155 (1985) |